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Searched refs:PIXCLK_RESYNC_CNTL (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
59 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
80 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
89 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
104 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
119 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
134 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
152 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
175 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
222 uint32_t PIXCLK_RESYNC_CNTL; member
Ddce_clock_source.c835 REG_UPDATE_2(PIXCLK_RESYNC_CNTL, in dce112_program_pixel_clk_resync()
839 REG_UPDATE(PIXCLK_RESYNC_CNTL, in dce112_program_pixel_clk_resync()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource.h195 SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \