Searched refs:PHY_CTRL4 (Results 1 – 3 of 3) sorted by relevance
| /linux-6.12.1/drivers/phy/qualcomm/ |
| D | phy-qcom-usb-ss.c | 23 #define PHY_CTRL4 0x7C macro
108 qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); in qcom_ssphy_power_on()
110 qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); in qcom_ssphy_power_on()
125 qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); in qcom_ssphy_power_off()
127 qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); in qcom_ssphy_power_off()
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| /linux-6.12.1/drivers/mmc/host/ |
| D | sdhci_am654.c | 33 #define PHY_CTRL4 0x10C macro
248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_am654_write_itapdly()
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, in sdhci_am654_write_itapdly()
252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, in sdhci_am654_write_itapdly()
254 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); in sdhci_am654_write_itapdly()
301 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); in sdhci_am654_set_clock()
349 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_j721e_4bit_set_clock()
351 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); in sdhci_j721e_4bit_set_clock()
352 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); in sdhci_j721e_4bit_set_clock()
741 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); in sdhci_am654_init()
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| /linux-6.12.1/drivers/phy/freescale/ |
| D | phy-fsl-imx8mq-usb.c | 37 #define PHY_CTRL4 0x10 macro
200 value = readl(imx_phy->base + PHY_CTRL4); in imx8m_phy_tune()
204 writel(value, imx_phy->base + PHY_CTRL4); in imx8m_phy_tune()
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