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Searched refs:PHYESYMCLK_CLOCK_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
Ddcn31_dccg.h42 SR(PHYESYMCLK_CLOCK_CNTL),\
93 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
94 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
Ddcn31_dccg.c522 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
529 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
Ddcn314_dccg.h47 SR(PHYESYMCLK_CLOCK_CNTL),\
184 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
185 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
Ddcn32_dccg.h55 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
56 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
Ddcn35_dccg.h147 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN, mask_sh),\
148 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_SRC_SEL, mask_sh),\
Ddcn35_dccg.c726 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN, in dccg35_set_physymclk_src_new()
1601 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, in dccg35_set_physymclk()
1605 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, in dccg35_set_physymclk()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
Ddcn20_dccg.h393 uint32_t PHYESYMCLK_CLOCK_CNTL; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource.h1236 SR(PHYESYMCLK_CLOCK_CNTL), SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \