Searched refs:PHYBSYMCLK_CLOCK_CNTL (Results 1 – 12 of 12) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
D | dcn30_dccg.h | 40 SR(PHYBSYMCLK_CLOCK_CNTL),\ 49 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ 50 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
D | dcn31_dccg.h | 39 SR(PHYBSYMCLK_CLOCK_CNTL),\ 87 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ 88 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
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D | dcn31_dccg.c | 471 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, in dccg31_set_physymclk() 478 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
D | dcn35_dccg.h | 62 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\ 63 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\ 141 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\ 142 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\
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D | dcn35_dccg.c | 708 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, in dccg35_set_physymclk_src_new() 1568 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, in dccg35_set_physymclk() 1572 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, in dccg35_set_physymclk()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
D | dcn314_dccg.h | 44 SR(PHYBSYMCLK_CLOCK_CNTL),\ 178 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ 179 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
D | dcn32_dccg.h | 49 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ 50 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
D | dcn401_dccg.h | 49 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\ 50 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\
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D | dcn401_dccg.c | 296 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, in dccg401_set_physymclk() 303 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
D | dcn20_dccg.h | 390 uint32_t PHYBSYMCLK_CLOCK_CNTL; member
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
D | dcn401_resource.h | 620 SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
D | dcn32_resource.h | 1234 SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \
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