| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | s3c64xx.dtsi | 135 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | samsung,s3c64xx-clock.h | 87 #define PCLK_UART1 72 macro
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| D | rk3036-cru.h | 69 #define PCLK_UART1 342 macro
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| D | exynos7-clk.h | 93 #define PCLK_UART1 1 macro
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| D | rk3188-cru-common.h | 85 #define PCLK_UART1 333 macro
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| D | rk3128-cru.h | 109 #define PCLK_UART1 342 macro
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| D | rk3228-cru.h | 108 #define PCLK_UART1 342 macro
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| D | rk3308-cru.h | 177 #define PCLK_UART1 198 macro
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| D | rv1108-cru.h | 117 #define PCLK_UART1 266 macro
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| D | rk3368-cru.h | 126 #define PCLK_UART1 342 macro
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| D | rk3288-cru.h | 134 #define PCLK_UART1 342 macro
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| D | rk3328-cru.h | 142 #define PCLK_UART1 211 macro
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| D | px30-cru.h | 152 #define PCLK_UART1 329 macro
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| D | rockchip,rk3576-cru.h | 514 #define PCLK_UART1 496 macro
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| D | rockchip,rv1126-cru.h | 45 #define PCLK_UART1 32 macro
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| D | rk3399-cru.h | 248 #define PCLK_UART1 353 macro
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| D | rockchip,rk3588-cru.h | 174 #define PCLK_UART1 159 macro
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| D | rk3568-cru.h | 348 #define PCLK_UART1 284 macro
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 243 GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
348 ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-rk3188.c | 653 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
744 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
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| D | clk-rk3036.c | 418 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
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| D | clk-rk3128.c | 503 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
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| D | clk-rk3228.c | 614 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
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| D | clk-rv1108.c | 607 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
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| /linux-6.12.1/arch/arm/boot/dts/rockchip/ |
| D | rk3xxx.dtsi | 125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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