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Searched refs:PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_sh_mask.h7947 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x1 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h2050 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_9_1_sh_mask.h1906 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_9_4_3_sh_mask.h2025 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_9_2_1_sh_mask.h1921 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_9_4_2_sh_mask.h15446 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_11_0_0_sh_mask.h24331 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_12_0_0_sh_mask.h32089 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_11_0_3_sh_mask.h26683 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_10_1_0_sh_mask.h7628 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro
Dgc_10_3_0_sh_mask.h7949 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK … macro