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Searched refs:PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h18078 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_9_1_sh_mask.h19385 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_9_4_3_sh_mask.h21406 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_9_2_1_sh_mask.h19278 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_9_4_2_sh_mask.h11521 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_11_5_0_sh_mask.h19066 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_11_0_0_sh_mask.h23086 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_12_0_0_sh_mask.h31106 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_11_0_3_sh_mask.h25430 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_10_1_0_sh_mask.h25641 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro
Dgc_10_3_0_sh_mask.h23842 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT … macro