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Searched refs:Op0 (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/arch/arm64/kvm/
Dsys_regs.h17 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
21 u8 Op0; member
31 ((struct sys_reg_params){ .Op0 = sys_reg_Op0(reg), \
38 ((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, \
63 u8 Op0; member
111 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_msg()
187 if (i1->Op0 != i2->Op0) in cmp_sys_reg()
188 return i1->Op0 - i2->Op0; in cmp_sys_reg()
231 #define Op0(_x) .Op0 = _x macro
239 Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
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Dtrace_handle_exit.h168 __field(u8, Op0)
179 __entry->Op0 = reg->Op0;
180 __entry->Op0 = reg->Op0;
189 __entry->Op0, __entry->Op1, __entry->CRn,
Dsys_regs.c455 if (p->Op0 == 0) { /* AArch32 */ in access_gic_sgi()
2159 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
2878 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); in handle_at_s1e01()
2888 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); in handle_at_s1e2()
2905 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); in handle_at_s12()
2931 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); in handle_alle1is()
3023 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); in handle_vmalls12e1is()
3047 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); in handle_ripas2e1is()
3122 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); in handle_ipas2e1is()
3148 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); in handle_tlbi_el1()
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Demulate-nested.c2053 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2); in populate_sysreg_config()
2277 if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011)) in triage_sysreg_trap()
/linux-6.12.1/arch/arm64/kvm/hyp/nvhe/
Dsys_regs.c327 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
/linux-6.12.1/Documentation/arch/arm64/
Dcpu-feature-registers.rst95 Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7