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Searched refs:OTG_CLOCK_CONTROL (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn314/
Ddcn314_optc.c145 REG_WAIT(OTG_CLOCK_CONTROL, in optc314_disable_crtc()
160 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc314_phantom_crtc_post_enable()
Ddcn314_optc.h67 SRI(OTG_CLOCK_CONTROL, OTG, inst),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn31/
Ddcn31_optc.c145 REG_WAIT(OTG_CLOCK_CONTROL, in optc31_disable_crtc()
168 REG_WAIT(OTG_CLOCK_CONTROL, in optc31_immediate_disable_crtc()
Ddcn31_optc.h66 SRI(OTG_CLOCK_CONTROL, OTG, inst),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn32/
Ddcn32_optc.c195 REG_WAIT(OTG_CLOCK_CONTROL, in optc32_disable_crtc()
210 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc32_phantom_crtc_post_enable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn35/
Ddcn35_optc.c162 REG_WAIT(OTG_CLOCK_CONTROL, in optc35_disable_crtc()
178 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc35_phantom_crtc_post_enable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn401/
Ddcn401_optc.c230 REG_WAIT(OTG_CLOCK_CONTROL, in optc401_disable_crtc()
245 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc401_phantom_crtc_post_enable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn10/
Ddcn10_optc.c497 REG_UPDATE_2(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
500 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
509 REG_UPDATE_2(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
571 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_disable_crtc()
Ddcn10_optc.h68 SRI(OTG_CLOCK_CONTROL, OTG, inst),\
147 uint32_t OTG_CLOCK_CONTROL; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/
Ddcn35_resource.h254 SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn30/
Ddcn30_optc.h71 SRI(OTG_CLOCK_CONTROL, OTG, inst),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.h507 SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource.h1025 SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \