/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
D | smu9_driver_if.h | 41 #define NUM_UCLK_DPM_LEVELS 4 macro 50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 221 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */ 222 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */ 223 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
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D | smu11_driver_if.h | 42 #define NUM_UCLK_DPM_LEVELS 4 macro 57 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 425 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
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/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
D | smu13_driver_if_v13_0_0.h | 42 #define NUM_UCLK_DPM_LEVELS 4 macro 1045 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1117 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz 1121 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1122 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:… 1124 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1125 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1405 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1568 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1569 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; [all …]
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D | smu13_driver_if_v13_0_7.h | 43 #define NUM_UCLK_DPM_LEVELS 4 macro 1054 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1117 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz 1123 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1124 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:… 1126 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1127 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1398 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1558 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1559 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; [all …]
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D | smu14_driver_if_v14_0.h | 40 #define NUM_UCLK_DPM_LEVELS 6 macro 1144 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1145 uint16_t FreqTableShadowUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1219 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 6 Primary SW DPM states (6 … 1220 …uint8_t UclkDpmShadowPstates [NUM_UCLK_DPM_LEVELS]; // 6 Shadow SW DPM states (6 … 1221 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1… 1222 …uint8_t FreqTableShadowUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1… 1223 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1224 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1630 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz [all …]
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D | smu11_driver_if_sienna_cichlid.h | 45 #define NUM_UCLK_DPM_LEVELS 4 macro 64 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 685 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 698 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, … 707 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 708 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 747 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1045 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1058 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, … 1067 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) [all …]
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D | smu11_driver_if_navi10.h | 45 #define NUM_UCLK_DPM_LEVELS 4 macro 60 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 589 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 599 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, … 604 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 605 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
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D | smu13_driver_if_aldebaran.h | 33 #define NUM_UCLK_DPM_LEVELS 4 macro 304 uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK 305 uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK
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D | smu11_driver_if_arcturus.h | 39 #define NUM_UCLK_DPM_LEVELS 4 macro 49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 519 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
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D | smu_v13_0_6_pmfw.h | 30 #define NUM_UCLK_DPM_LEVELS 4 macro
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/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/ |
D | smu9_driver_if.h | 40 #define NUM_UCLK_DPM_LEVELS 4 macro 53 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 313 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
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/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
D | sienna_cichlid_ppt.c | 2750 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 2768 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 2783 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 2787 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 2833 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 3389 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable() 3407 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable() 3422 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable() 3426 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable() 3472 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
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D | arcturus_ppt.c | 1758 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
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/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
D | vega20_processpptables.c | 332 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
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D | vega10_hwmgr.c | 1898 while (i < NUM_UCLK_DPM_LEVELS) { in vega10_populate_all_memory_levels() 3637 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; in vega10_get_soc_index_for_max_uclk() 3663 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) in vega10_upload_dpm_bootup_level()
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D | vega12_hwmgr.c | 2528 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega12_set_uclk_to_highest_dpm_level()
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D | vega20_hwmgr.c | 3594 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega20_set_uclk_to_highest_dpm_level()
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