1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Hardware driver for DAQ-STC based boards
4 *
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 */
9
10 /*
11 * This file is meant to be included by another file, e.g.,
12 * ni_atmio.c or ni_pcimio.c.
13 *
14 * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
15 *
16 * References (ftp://ftp.natinst.com/support/manuals):
17 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
18 * 341079b.pdf PCI E Series RLPM
19 * 340934b.pdf DAQ-STC reference manual
20 *
21 * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
22 * release_ni611x.pdf
23 * release_ni67xx.pdf
24 *
25 * Other possibly relevant info:
26 * 320517c.pdf User manual (obsolete)
27 * 320517f.pdf User manual (new)
28 * 320889a.pdf delete
29 * 320906c.pdf maximum signal ratings
30 * 321066a.pdf about 16x
31 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
32 * 321808a.pdf about at-mio-16e-10 rev P
33 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
34 * 321838a.pdf about at-mio-16de-10 rev N
35 *
36 * ISSUES:
37 * - the interrupt routine needs to be cleaned up
38 *
39 * 2006-02-07: S-Series PCI-6143: Support has been added but is not
40 * fully tested as yet. Terry Barnaby, BEAM Ltd.
41 */
42
43 #include <linux/interrupt.h>
44 #include <linux/sched.h>
45 #include <linux/delay.h>
46 #include <linux/comedi/comedi_8255.h>
47 #include "mite.h"
48
49 #ifdef PCIDMA
50 #define IS_PCIMIO 1
51 #else
52 #define IS_PCIMIO 0
53 #endif
54
55 /* A timeout count */
56 #define NI_TIMEOUT 1000
57
58 /* Note: this table must match the ai_gain_* definitions */
59 static const short ni_gainlkup[][16] = {
60 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
61 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
62 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
63 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
64 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
65 [ai_gain_4] = {0, 1, 4, 7},
66 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
67 0x003, 0x004, 0x005, 0x006},
68 [ai_gain_622x] = {0, 1, 4, 5},
69 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
70 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
71 };
72
73 static const struct comedi_lrange range_ni_E_ai = {
74 16, {
75 BIP_RANGE(10),
76 BIP_RANGE(5),
77 BIP_RANGE(2.5),
78 BIP_RANGE(1),
79 BIP_RANGE(0.5),
80 BIP_RANGE(0.25),
81 BIP_RANGE(0.1),
82 BIP_RANGE(0.05),
83 UNI_RANGE(20),
84 UNI_RANGE(10),
85 UNI_RANGE(5),
86 UNI_RANGE(2),
87 UNI_RANGE(1),
88 UNI_RANGE(0.5),
89 UNI_RANGE(0.2),
90 UNI_RANGE(0.1)
91 }
92 };
93
94 static const struct comedi_lrange range_ni_E_ai_limited = {
95 8, {
96 BIP_RANGE(10),
97 BIP_RANGE(5),
98 BIP_RANGE(1),
99 BIP_RANGE(0.1),
100 UNI_RANGE(10),
101 UNI_RANGE(5),
102 UNI_RANGE(1),
103 UNI_RANGE(0.1)
104 }
105 };
106
107 static const struct comedi_lrange range_ni_E_ai_limited14 = {
108 14, {
109 BIP_RANGE(10),
110 BIP_RANGE(5),
111 BIP_RANGE(2),
112 BIP_RANGE(1),
113 BIP_RANGE(0.5),
114 BIP_RANGE(0.2),
115 BIP_RANGE(0.1),
116 UNI_RANGE(10),
117 UNI_RANGE(5),
118 UNI_RANGE(2),
119 UNI_RANGE(1),
120 UNI_RANGE(0.5),
121 UNI_RANGE(0.2),
122 UNI_RANGE(0.1)
123 }
124 };
125
126 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
127 4, {
128 BIP_RANGE(10),
129 BIP_RANGE(5),
130 BIP_RANGE(0.5),
131 BIP_RANGE(0.05)
132 }
133 };
134
135 static const struct comedi_lrange range_ni_E_ai_611x = {
136 8, {
137 BIP_RANGE(50),
138 BIP_RANGE(20),
139 BIP_RANGE(10),
140 BIP_RANGE(5),
141 BIP_RANGE(2),
142 BIP_RANGE(1),
143 BIP_RANGE(0.5),
144 BIP_RANGE(0.2)
145 }
146 };
147
148 static const struct comedi_lrange range_ni_M_ai_622x = {
149 4, {
150 BIP_RANGE(10),
151 BIP_RANGE(5),
152 BIP_RANGE(1),
153 BIP_RANGE(0.2)
154 }
155 };
156
157 static const struct comedi_lrange range_ni_M_ai_628x = {
158 7, {
159 BIP_RANGE(10),
160 BIP_RANGE(5),
161 BIP_RANGE(2),
162 BIP_RANGE(1),
163 BIP_RANGE(0.5),
164 BIP_RANGE(0.2),
165 BIP_RANGE(0.1)
166 }
167 };
168
169 static const struct comedi_lrange *const ni_range_lkup[] = {
170 [ai_gain_16] = &range_ni_E_ai,
171 [ai_gain_8] = &range_ni_E_ai_limited,
172 [ai_gain_14] = &range_ni_E_ai_limited14,
173 [ai_gain_4] = &range_ni_E_ai_bipolar4,
174 [ai_gain_611x] = &range_ni_E_ai_611x,
175 [ai_gain_622x] = &range_ni_M_ai_622x,
176 [ai_gain_628x] = &range_ni_M_ai_628x,
177 [ai_gain_6143] = &range_bipolar5
178 };
179
180 enum aimodes {
181 AIMODE_NONE = 0,
182 AIMODE_HALF_FULL = 1,
183 AIMODE_SCAN = 2,
184 AIMODE_SAMPLE = 3,
185 };
186
187 enum ni_common_subdevices {
188 NI_AI_SUBDEV,
189 NI_AO_SUBDEV,
190 NI_DIO_SUBDEV,
191 NI_8255_DIO_SUBDEV,
192 NI_UNUSED_SUBDEV,
193 NI_CALIBRATION_SUBDEV,
194 NI_EEPROM_SUBDEV,
195 NI_PFI_DIO_SUBDEV,
196 NI_CS5529_CALIBRATION_SUBDEV,
197 NI_SERIAL_SUBDEV,
198 NI_RTSI_SUBDEV,
199 NI_GPCT0_SUBDEV,
200 NI_GPCT1_SUBDEV,
201 NI_FREQ_OUT_SUBDEV,
202 NI_NUM_SUBDEVICES
203 };
204
205 #define NI_GPCT_SUBDEV(x) (NI_GPCT0_SUBDEV + (x))
206
207 enum timebase_nanoseconds {
208 TIMEBASE_1_NS = 50,
209 TIMEBASE_2_NS = 10000
210 };
211
212 #define SERIAL_DISABLED 0
213 #define SERIAL_600NS 600
214 #define SERIAL_1_2US 1200
215 #define SERIAL_10US 10000
216
217 static const int num_adc_stages_611x = 3;
218
219 #ifdef PCIDMA
220
ni_writel(struct comedi_device * dev,unsigned int data,int reg)221 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
222 {
223 writel(data, dev->mmio + reg);
224 }
225
ni_writew(struct comedi_device * dev,unsigned int data,int reg)226 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
227 {
228 writew(data, dev->mmio + reg);
229 }
230
ni_writeb(struct comedi_device * dev,unsigned int data,int reg)231 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
232 {
233 writeb(data, dev->mmio + reg);
234 }
235
ni_readl(struct comedi_device * dev,int reg)236 static unsigned int ni_readl(struct comedi_device *dev, int reg)
237 {
238 return readl(dev->mmio + reg);
239 }
240
ni_readw(struct comedi_device * dev,int reg)241 static unsigned int ni_readw(struct comedi_device *dev, int reg)
242 {
243 return readw(dev->mmio + reg);
244 }
245
ni_readb(struct comedi_device * dev,int reg)246 static unsigned int ni_readb(struct comedi_device *dev, int reg)
247 {
248 return readb(dev->mmio + reg);
249 }
250
251 #else /* PCIDMA */
252
ni_writel(struct comedi_device * dev,unsigned int data,int reg)253 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
254 {
255 outl(data, dev->iobase + reg);
256 }
257
ni_writew(struct comedi_device * dev,unsigned int data,int reg)258 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
259 {
260 outw(data, dev->iobase + reg);
261 }
262
ni_writeb(struct comedi_device * dev,unsigned int data,int reg)263 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
264 {
265 outb(data, dev->iobase + reg);
266 }
267
ni_readl(struct comedi_device * dev,int reg)268 static unsigned int ni_readl(struct comedi_device *dev, int reg)
269 {
270 return inl(dev->iobase + reg);
271 }
272
ni_readw(struct comedi_device * dev,int reg)273 static unsigned int ni_readw(struct comedi_device *dev, int reg)
274 {
275 return inw(dev->iobase + reg);
276 }
277
ni_readb(struct comedi_device * dev,int reg)278 static unsigned int ni_readb(struct comedi_device *dev, int reg)
279 {
280 return inb(dev->iobase + reg);
281 }
282
283 #endif /* PCIDMA */
284
285 /*
286 * We automatically take advantage of STC registers that can be
287 * read/written directly in the I/O space of the board.
288 *
289 * The AT-MIO and DAQCard devices map the low 8 STC registers to
290 * iobase+reg*2.
291 *
292 * Most PCIMIO devices also map the low 8 STC registers but the
293 * 611x devices map the read registers to iobase+(addr-1)*2.
294 * For now non-windowed STC access is disabled if a PCIMIO device
295 * is detected (devpriv->mite has been initialized).
296 *
297 * The M series devices do not used windowed registers for the
298 * STC registers. The functions below handle the mapping of the
299 * windowed STC registers to the m series register offsets.
300 */
301
302 struct mio_regmap {
303 unsigned int mio_reg;
304 int size;
305 };
306
307 static const struct mio_regmap m_series_stc_write_regmap[] = {
308 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
309 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
310 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
311 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
312 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
313 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
314 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
315 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
316 /*
317 * NISTC_DIO_OUT_REG maps to:
318 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
319 */
320 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
321 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
322 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
323 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
324 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
325 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
326 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
327 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
328 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
329 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
330 [NISTC_G0_MODE_REG] = { 0x134, 2 },
331 [NISTC_G1_MODE_REG] = { 0x136, 2 },
332 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
333 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
334 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
335 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
336 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
337 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
338 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
339 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
340 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
341 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
342 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
343 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
344 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
345 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
346 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
347 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
348 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
349 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
350 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
351 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
352 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
353 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
354 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
355 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
356 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
357 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
358 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
359 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
360 [NISTC_RESET_REG] = { 0x190, 2 },
361 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
362 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
363 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
364 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
365 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
366 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
367 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
368 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
369 /* doc for following line: mhddk/nimseries/ChipObjects/tMSeries.h */
370 [NISTC_RTSI_BOARD_REG] = { 0x1a2, 2 },
371 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
372 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
373 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
374 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
375 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
376 };
377
m_series_stc_write(struct comedi_device * dev,unsigned int data,unsigned int reg)378 static void m_series_stc_write(struct comedi_device *dev,
379 unsigned int data, unsigned int reg)
380 {
381 const struct mio_regmap *regmap;
382
383 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
384 regmap = &m_series_stc_write_regmap[reg];
385 } else {
386 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
387 __func__, reg);
388 return;
389 }
390
391 switch (regmap->size) {
392 case 4:
393 ni_writel(dev, data, regmap->mio_reg);
394 break;
395 case 2:
396 ni_writew(dev, data, regmap->mio_reg);
397 break;
398 default:
399 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
400 __func__, reg);
401 break;
402 }
403 }
404
405 static const struct mio_regmap m_series_stc_read_regmap[] = {
406 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
407 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
408 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
409 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
410 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
411 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
412 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
413 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
414 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
415 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
416 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
417 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
418 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
419 [NISTC_STATUS1_REG] = { 0x136, 2 },
420 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
421 [NISTC_STATUS2_REG] = { 0x13a, 2 },
422 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
423 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
424 };
425
m_series_stc_read(struct comedi_device * dev,unsigned int reg)426 static unsigned int m_series_stc_read(struct comedi_device *dev,
427 unsigned int reg)
428 {
429 const struct mio_regmap *regmap;
430
431 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
432 regmap = &m_series_stc_read_regmap[reg];
433 } else {
434 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
435 __func__, reg);
436 return 0;
437 }
438
439 switch (regmap->size) {
440 case 4:
441 return ni_readl(dev, regmap->mio_reg);
442 case 2:
443 return ni_readw(dev, regmap->mio_reg);
444 case 1:
445 return ni_readb(dev, regmap->mio_reg);
446 default:
447 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
448 __func__, reg);
449 return 0;
450 }
451 }
452
ni_stc_writew(struct comedi_device * dev,unsigned int data,int reg)453 static void ni_stc_writew(struct comedi_device *dev,
454 unsigned int data, int reg)
455 {
456 struct ni_private *devpriv = dev->private;
457 unsigned long flags;
458
459 if (devpriv->is_m_series) {
460 m_series_stc_write(dev, data, reg);
461 } else {
462 spin_lock_irqsave(&devpriv->window_lock, flags);
463 if (!devpriv->mite && reg < 8) {
464 ni_writew(dev, data, reg * 2);
465 } else {
466 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
467 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
468 }
469 spin_unlock_irqrestore(&devpriv->window_lock, flags);
470 }
471 }
472
ni_stc_writel(struct comedi_device * dev,unsigned int data,int reg)473 static void ni_stc_writel(struct comedi_device *dev,
474 unsigned int data, int reg)
475 {
476 struct ni_private *devpriv = dev->private;
477
478 if (devpriv->is_m_series) {
479 m_series_stc_write(dev, data, reg);
480 } else {
481 ni_stc_writew(dev, data >> 16, reg);
482 ni_stc_writew(dev, data & 0xffff, reg + 1);
483 }
484 }
485
ni_stc_readw(struct comedi_device * dev,int reg)486 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
487 {
488 struct ni_private *devpriv = dev->private;
489 unsigned long flags;
490 unsigned int val;
491
492 if (devpriv->is_m_series) {
493 val = m_series_stc_read(dev, reg);
494 } else {
495 spin_lock_irqsave(&devpriv->window_lock, flags);
496 if (!devpriv->mite && reg < 8) {
497 val = ni_readw(dev, reg * 2);
498 } else {
499 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
500 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
501 }
502 spin_unlock_irqrestore(&devpriv->window_lock, flags);
503 }
504 return val;
505 }
506
ni_stc_readl(struct comedi_device * dev,int reg)507 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
508 {
509 struct ni_private *devpriv = dev->private;
510 unsigned int val;
511
512 if (devpriv->is_m_series) {
513 val = m_series_stc_read(dev, reg);
514 } else {
515 val = ni_stc_readw(dev, reg) << 16;
516 val |= ni_stc_readw(dev, reg + 1);
517 }
518 return val;
519 }
520
ni_set_bitfield(struct comedi_device * dev,int reg,unsigned int bit_mask,unsigned int bit_values)521 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
522 unsigned int bit_mask,
523 unsigned int bit_values)
524 {
525 struct ni_private *devpriv = dev->private;
526 unsigned long flags;
527
528 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
529 switch (reg) {
530 case NISTC_INTA_ENA_REG:
531 devpriv->int_a_enable_reg &= ~bit_mask;
532 devpriv->int_a_enable_reg |= bit_values & bit_mask;
533 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
534 break;
535 case NISTC_INTB_ENA_REG:
536 devpriv->int_b_enable_reg &= ~bit_mask;
537 devpriv->int_b_enable_reg |= bit_values & bit_mask;
538 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
539 break;
540 case NISTC_IO_BIDIR_PIN_REG:
541 devpriv->io_bidirection_pin_reg &= ~bit_mask;
542 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
543 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
544 break;
545 case NI_E_DMA_AI_AO_SEL_REG:
546 devpriv->ai_ao_select_reg &= ~bit_mask;
547 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
548 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
549 break;
550 case NI_E_DMA_G0_G1_SEL_REG:
551 devpriv->g0_g1_select_reg &= ~bit_mask;
552 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
553 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
554 break;
555 case NI_M_CDIO_DMA_SEL_REG:
556 devpriv->cdio_dma_select_reg &= ~bit_mask;
557 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
558 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
559 break;
560 default:
561 dev_err(dev->class_dev, "called with invalid register %d\n",
562 reg);
563 break;
564 }
565 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
566 }
567
568 #ifdef PCIDMA
569
570 /* selects the MITE channel to use for DMA */
571 #define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \
572 ((x) == 4) ? 0x3 : \
573 ((x) == 5) ? 0x5 : 0x0)
574
575 /* DMA channel setup */
ni_request_ai_mite_channel(struct comedi_device * dev)576 static int ni_request_ai_mite_channel(struct comedi_device *dev)
577 {
578 struct ni_private *devpriv = dev->private;
579 struct mite_channel *mite_chan;
580 unsigned long flags;
581 unsigned int bits;
582
583 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
584 mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
585 if (!mite_chan) {
586 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
587 dev_err(dev->class_dev,
588 "failed to reserve mite dma channel for analog input\n");
589 return -EBUSY;
590 }
591 mite_chan->dir = COMEDI_INPUT;
592 devpriv->ai_mite_chan = mite_chan;
593
594 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
595 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
596 NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
597
598 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
599 return 0;
600 }
601
ni_request_ao_mite_channel(struct comedi_device * dev)602 static int ni_request_ao_mite_channel(struct comedi_device *dev)
603 {
604 struct ni_private *devpriv = dev->private;
605 struct mite_channel *mite_chan;
606 unsigned long flags;
607 unsigned int bits;
608
609 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
610 mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
611 if (!mite_chan) {
612 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
613 dev_err(dev->class_dev,
614 "failed to reserve mite dma channel for analog output\n");
615 return -EBUSY;
616 }
617 mite_chan->dir = COMEDI_OUTPUT;
618 devpriv->ao_mite_chan = mite_chan;
619
620 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
621 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
622 NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
623
624 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
625 return 0;
626 }
627
ni_request_gpct_mite_channel(struct comedi_device * dev,unsigned int gpct_index,enum comedi_io_direction direction)628 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
629 unsigned int gpct_index,
630 enum comedi_io_direction direction)
631 {
632 struct ni_private *devpriv = dev->private;
633 struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
634 struct mite_channel *mite_chan;
635 unsigned long flags;
636 unsigned int bits;
637
638 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
639 mite_chan = mite_request_channel(devpriv->mite,
640 devpriv->gpct_mite_ring[gpct_index]);
641 if (!mite_chan) {
642 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
643 dev_err(dev->class_dev,
644 "failed to reserve mite dma channel for counter\n");
645 return -EBUSY;
646 }
647 mite_chan->dir = direction;
648 ni_tio_set_mite_channel(counter, mite_chan);
649
650 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
651 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
652 NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
653 NI_E_DMA_G0_G1_SEL(gpct_index, bits));
654
655 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
656 return 0;
657 }
658
ni_request_cdo_mite_channel(struct comedi_device * dev)659 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
660 {
661 struct ni_private *devpriv = dev->private;
662 struct mite_channel *mite_chan;
663 unsigned long flags;
664 unsigned int bits;
665
666 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
667 mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
668 if (!mite_chan) {
669 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
670 dev_err(dev->class_dev,
671 "failed to reserve mite dma channel for correlated digital output\n");
672 return -EBUSY;
673 }
674 mite_chan->dir = COMEDI_OUTPUT;
675 devpriv->cdo_mite_chan = mite_chan;
676
677 /*
678 * XXX just guessing NI_STC_DMA_CHAN_SEL()
679 * returns the right bits, under the assumption the cdio dma
680 * selection works just like ai/ao/gpct.
681 * Definitely works for dma channels 0 and 1.
682 */
683 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
684 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
685 NI_M_CDIO_DMA_SEL_CDO_MASK,
686 NI_M_CDIO_DMA_SEL_CDO(bits));
687
688 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
689 return 0;
690 }
691 #endif /* PCIDMA */
692
ni_release_ai_mite_channel(struct comedi_device * dev)693 static void ni_release_ai_mite_channel(struct comedi_device *dev)
694 {
695 #ifdef PCIDMA
696 struct ni_private *devpriv = dev->private;
697 unsigned long flags;
698
699 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
700 if (devpriv->ai_mite_chan) {
701 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
702 NI_E_DMA_AI_SEL_MASK, 0);
703 mite_release_channel(devpriv->ai_mite_chan);
704 devpriv->ai_mite_chan = NULL;
705 }
706 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
707 #endif /* PCIDMA */
708 }
709
ni_release_ao_mite_channel(struct comedi_device * dev)710 static void ni_release_ao_mite_channel(struct comedi_device *dev)
711 {
712 #ifdef PCIDMA
713 struct ni_private *devpriv = dev->private;
714 unsigned long flags;
715
716 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
717 if (devpriv->ao_mite_chan) {
718 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
719 NI_E_DMA_AO_SEL_MASK, 0);
720 mite_release_channel(devpriv->ao_mite_chan);
721 devpriv->ao_mite_chan = NULL;
722 }
723 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
724 #endif /* PCIDMA */
725 }
726
727 #ifdef PCIDMA
ni_release_gpct_mite_channel(struct comedi_device * dev,unsigned int gpct_index)728 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
729 unsigned int gpct_index)
730 {
731 struct ni_private *devpriv = dev->private;
732 unsigned long flags;
733
734 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
735 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
736 struct mite_channel *mite_chan =
737 devpriv->counter_dev->counters[gpct_index].mite_chan;
738
739 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
740 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
741 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
742 NULL);
743 mite_release_channel(mite_chan);
744 }
745 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
746 }
747
ni_release_cdo_mite_channel(struct comedi_device * dev)748 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
749 {
750 struct ni_private *devpriv = dev->private;
751 unsigned long flags;
752
753 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
754 if (devpriv->cdo_mite_chan) {
755 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
756 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
757 mite_release_channel(devpriv->cdo_mite_chan);
758 devpriv->cdo_mite_chan = NULL;
759 }
760 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
761 }
762
ni_e_series_enable_second_irq(struct comedi_device * dev,unsigned int gpct_index,short enable)763 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
764 unsigned int gpct_index, short enable)
765 {
766 struct ni_private *devpriv = dev->private;
767 unsigned int val = 0;
768 int reg;
769
770 if (devpriv->is_m_series || gpct_index > 1)
771 return;
772
773 /*
774 * e-series boards use the second irq signals to generate
775 * dma requests for their counters
776 */
777 if (gpct_index == 0) {
778 reg = NISTC_INTA2_ENA_REG;
779 if (enable)
780 val = NISTC_INTA_ENA_G0_GATE;
781 } else {
782 reg = NISTC_INTB2_ENA_REG;
783 if (enable)
784 val = NISTC_INTB_ENA_G1_GATE;
785 }
786 ni_stc_writew(dev, val, reg);
787 }
788 #endif /* PCIDMA */
789
ni_clear_ai_fifo(struct comedi_device * dev)790 static void ni_clear_ai_fifo(struct comedi_device *dev)
791 {
792 struct ni_private *devpriv = dev->private;
793 static const int timeout = 10000;
794 int i;
795
796 if (devpriv->is_6143) {
797 /* Flush the 6143 data FIFO */
798 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
799 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
800 /* Wait for complete */
801 for (i = 0; i < timeout; i++) {
802 if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
803 break;
804 udelay(1);
805 }
806 if (i == timeout)
807 dev_err(dev->class_dev, "FIFO flush timeout\n");
808 } else {
809 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
810 if (devpriv->is_625x) {
811 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
812 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
813 #if 0
814 /*
815 * The NI example code does 3 convert pulses for 625x
816 * boards, But that appears to be wrong in practice.
817 */
818 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
819 NISTC_AI_CMD1_REG);
820 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
821 NISTC_AI_CMD1_REG);
822 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
823 NISTC_AI_CMD1_REG);
824 #endif
825 }
826 }
827 }
828
ni_ao_win_outw(struct comedi_device * dev,unsigned int data,int addr)829 static inline void ni_ao_win_outw(struct comedi_device *dev,
830 unsigned int data, int addr)
831 {
832 struct ni_private *devpriv = dev->private;
833 unsigned long flags;
834
835 spin_lock_irqsave(&devpriv->window_lock, flags);
836 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
837 ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
838 spin_unlock_irqrestore(&devpriv->window_lock, flags);
839 }
840
ni_ao_win_outl(struct comedi_device * dev,unsigned int data,int addr)841 static inline void ni_ao_win_outl(struct comedi_device *dev,
842 unsigned int data, int addr)
843 {
844 struct ni_private *devpriv = dev->private;
845 unsigned long flags;
846
847 spin_lock_irqsave(&devpriv->window_lock, flags);
848 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
849 ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
850 spin_unlock_irqrestore(&devpriv->window_lock, flags);
851 }
852
ni_ao_win_inw(struct comedi_device * dev,int addr)853 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
854 {
855 struct ni_private *devpriv = dev->private;
856 unsigned long flags;
857 unsigned short data;
858
859 spin_lock_irqsave(&devpriv->window_lock, flags);
860 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
861 data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
862 spin_unlock_irqrestore(&devpriv->window_lock, flags);
863 return data;
864 }
865
866 /*
867 * ni_set_bits( ) allows different parts of the ni_mio_common driver to
868 * share registers (such as Interrupt_A_Register) without interfering with
869 * each other.
870 *
871 * NOTE: the switch/case statements are optimized out for a constant argument
872 * so this is actually quite fast--- If you must wrap another function around
873 * this make it inline to avoid a large speed penalty.
874 *
875 * value should only be 1 or 0.
876 */
ni_set_bits(struct comedi_device * dev,int reg,unsigned int bits,unsigned int value)877 static inline void ni_set_bits(struct comedi_device *dev, int reg,
878 unsigned int bits, unsigned int value)
879 {
880 unsigned int bit_values;
881
882 if (value)
883 bit_values = bits;
884 else
885 bit_values = 0;
886 ni_set_bitfield(dev, reg, bits, bit_values);
887 }
888
889 #ifdef PCIDMA
ni_sync_ai_dma(struct comedi_device * dev)890 static void ni_sync_ai_dma(struct comedi_device *dev)
891 {
892 struct ni_private *devpriv = dev->private;
893 struct comedi_subdevice *s = dev->read_subdev;
894 unsigned long flags;
895
896 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
897 if (devpriv->ai_mite_chan)
898 mite_sync_dma(devpriv->ai_mite_chan, s);
899 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
900 }
901
ni_ai_drain_dma(struct comedi_device * dev)902 static int ni_ai_drain_dma(struct comedi_device *dev)
903 {
904 struct ni_private *devpriv = dev->private;
905 int i;
906 static const int timeout = 10000;
907 unsigned long flags;
908 int retval = 0;
909
910 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
911 if (devpriv->ai_mite_chan) {
912 for (i = 0; i < timeout; i++) {
913 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
914 NISTC_AI_STATUS1_FIFO_E) &&
915 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
916 break;
917 udelay(5);
918 }
919 if (i == timeout) {
920 dev_err(dev->class_dev, "timed out\n");
921 dev_err(dev->class_dev,
922 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
923 mite_bytes_in_transit(devpriv->ai_mite_chan),
924 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
925 retval = -1;
926 }
927 }
928 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
929
930 ni_sync_ai_dma(dev);
931
932 return retval;
933 }
934
ni_ao_wait_for_dma_load(struct comedi_device * dev)935 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
936 {
937 static const int timeout = 10000;
938 int i;
939
940 for (i = 0; i < timeout; i++) {
941 unsigned short b_status;
942
943 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
944 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
945 break;
946 /*
947 * If we poll too often, the pci bus activity seems
948 * to slow the dma transfer down.
949 */
950 usleep_range(10, 100);
951 }
952 if (i == timeout) {
953 dev_err(dev->class_dev, "timed out waiting for dma load\n");
954 return -EPIPE;
955 }
956 return 0;
957 }
958 #endif /* PCIDMA */
959
960 #ifndef PCIDMA
961
ni_ao_fifo_load(struct comedi_device * dev,struct comedi_subdevice * s,int n)962 static void ni_ao_fifo_load(struct comedi_device *dev,
963 struct comedi_subdevice *s, int n)
964 {
965 struct ni_private *devpriv = dev->private;
966 int i;
967 unsigned short d;
968 unsigned int packed_data;
969
970 for (i = 0; i < n; i++) {
971 comedi_buf_read_samples(s, &d, 1);
972
973 if (devpriv->is_6xxx) {
974 packed_data = d & 0xffff;
975 /* 6711 only has 16 bit wide ao fifo */
976 if (!devpriv->is_6711) {
977 comedi_buf_read_samples(s, &d, 1);
978 i++;
979 packed_data |= (d << 16) & 0xffff0000;
980 }
981 ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
982 } else {
983 ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
984 }
985 }
986 }
987
988 /*
989 * There's a small problem if the FIFO gets really low and we
990 * don't have the data to fill it. Basically, if after we fill
991 * the FIFO with all the data available, the FIFO is _still_
992 * less than half full, we never clear the interrupt. If the
993 * IRQ is in edge mode, we never get another interrupt, because
994 * this one wasn't cleared. If in level mode, we get flooded
995 * with interrupts that we can't fulfill, because nothing ever
996 * gets put into the buffer.
997 *
998 * This kind of situation is recoverable, but it is easier to
999 * just pretend we had a FIFO underrun, since there is a good
1000 * chance it will happen anyway. This is _not_ the case for
1001 * RT code, as RT code might purposely be running close to the
1002 * metal. Needs to be fixed eventually.
1003 */
ni_ao_fifo_half_empty(struct comedi_device * dev,struct comedi_subdevice * s)1004 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1005 struct comedi_subdevice *s)
1006 {
1007 const struct ni_board_struct *board = dev->board_ptr;
1008 unsigned int nbytes;
1009 unsigned int nsamples;
1010
1011 nbytes = comedi_buf_read_n_available(s);
1012 if (nbytes == 0) {
1013 s->async->events |= COMEDI_CB_OVERFLOW;
1014 return 0;
1015 }
1016
1017 nsamples = comedi_bytes_to_samples(s, nbytes);
1018 if (nsamples > board->ao_fifo_depth / 2)
1019 nsamples = board->ao_fifo_depth / 2;
1020
1021 ni_ao_fifo_load(dev, s, nsamples);
1022
1023 return 1;
1024 }
1025
ni_ao_prep_fifo(struct comedi_device * dev,struct comedi_subdevice * s)1026 static int ni_ao_prep_fifo(struct comedi_device *dev,
1027 struct comedi_subdevice *s)
1028 {
1029 const struct ni_board_struct *board = dev->board_ptr;
1030 struct ni_private *devpriv = dev->private;
1031 unsigned int nbytes;
1032 unsigned int nsamples;
1033
1034 /* reset fifo */
1035 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1036 if (devpriv->is_6xxx)
1037 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1038
1039 /* load some data */
1040 nbytes = comedi_buf_read_n_available(s);
1041 if (nbytes == 0)
1042 return 0;
1043
1044 nsamples = comedi_bytes_to_samples(s, nbytes);
1045 if (nsamples > board->ao_fifo_depth)
1046 nsamples = board->ao_fifo_depth;
1047
1048 ni_ao_fifo_load(dev, s, nsamples);
1049
1050 return nsamples;
1051 }
1052
ni_ai_fifo_read(struct comedi_device * dev,struct comedi_subdevice * s,int n)1053 static void ni_ai_fifo_read(struct comedi_device *dev,
1054 struct comedi_subdevice *s, int n)
1055 {
1056 struct ni_private *devpriv = dev->private;
1057 struct comedi_async *async = s->async;
1058 unsigned int dl;
1059 unsigned short data;
1060 int i;
1061
1062 if (devpriv->is_611x) {
1063 for (i = 0; i < n / 2; i++) {
1064 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1065 /* This may get the hi/lo data in the wrong order */
1066 data = (dl >> 16) & 0xffff;
1067 comedi_buf_write_samples(s, &data, 1);
1068 data = dl & 0xffff;
1069 comedi_buf_write_samples(s, &data, 1);
1070 }
1071 /* Check if there's a single sample stuck in the FIFO */
1072 if (n % 2) {
1073 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1074 data = dl & 0xffff;
1075 comedi_buf_write_samples(s, &data, 1);
1076 }
1077 } else if (devpriv->is_6143) {
1078 /*
1079 * This just reads the FIFO assuming the data is present,
1080 * no checks on the FIFO status are performed.
1081 */
1082 for (i = 0; i < n / 2; i++) {
1083 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1084
1085 data = (dl >> 16) & 0xffff;
1086 comedi_buf_write_samples(s, &data, 1);
1087 data = dl & 0xffff;
1088 comedi_buf_write_samples(s, &data, 1);
1089 }
1090 if (n % 2) {
1091 /* Assume there is a single sample stuck in the FIFO */
1092 /* Get stranded sample into FIFO */
1093 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1094 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1095 data = (dl >> 16) & 0xffff;
1096 comedi_buf_write_samples(s, &data, 1);
1097 }
1098 } else {
1099 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1100 dev_err(dev->class_dev,
1101 "bug! ai_fifo_buffer too small\n");
1102 async->events |= COMEDI_CB_ERROR;
1103 return;
1104 }
1105 for (i = 0; i < n; i++) {
1106 devpriv->ai_fifo_buffer[i] =
1107 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1108 }
1109 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1110 }
1111 }
1112
ni_handle_fifo_half_full(struct comedi_device * dev)1113 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1114 {
1115 const struct ni_board_struct *board = dev->board_ptr;
1116 struct comedi_subdevice *s = dev->read_subdev;
1117 int n;
1118
1119 n = board->ai_fifo_depth / 2;
1120
1121 ni_ai_fifo_read(dev, s, n);
1122 }
1123 #endif
1124
1125 /* Empties the AI fifo */
ni_handle_fifo_dregs(struct comedi_device * dev)1126 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1127 {
1128 struct ni_private *devpriv = dev->private;
1129 struct comedi_subdevice *s = dev->read_subdev;
1130 unsigned int dl;
1131 unsigned short data;
1132 int i;
1133
1134 if (devpriv->is_611x) {
1135 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1136 NISTC_AI_STATUS1_FIFO_E) == 0) {
1137 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1138
1139 /* This may get the hi/lo data in the wrong order */
1140 data = dl >> 16;
1141 comedi_buf_write_samples(s, &data, 1);
1142 data = dl & 0xffff;
1143 comedi_buf_write_samples(s, &data, 1);
1144 }
1145 } else if (devpriv->is_6143) {
1146 i = 0;
1147 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1148 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1149
1150 /* This may get the hi/lo data in the wrong order */
1151 data = dl >> 16;
1152 comedi_buf_write_samples(s, &data, 1);
1153 data = dl & 0xffff;
1154 comedi_buf_write_samples(s, &data, 1);
1155 i += 2;
1156 }
1157 /* Check if stranded sample is present */
1158 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1159 /* Get stranded sample into FIFO */
1160 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1161 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1162 data = (dl >> 16) & 0xffff;
1163 comedi_buf_write_samples(s, &data, 1);
1164 }
1165
1166 } else {
1167 unsigned short fe; /* fifo empty */
1168
1169 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1170 NISTC_AI_STATUS1_FIFO_E;
1171 while (fe == 0) {
1172 for (i = 0;
1173 i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1174 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1175 NISTC_AI_STATUS1_FIFO_E;
1176 if (fe)
1177 break;
1178 devpriv->ai_fifo_buffer[i] =
1179 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1180 }
1181 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1182 }
1183 }
1184 }
1185
get_last_sample_611x(struct comedi_device * dev)1186 static void get_last_sample_611x(struct comedi_device *dev)
1187 {
1188 struct ni_private *devpriv = dev->private;
1189 struct comedi_subdevice *s = dev->read_subdev;
1190 unsigned short data;
1191 unsigned int dl;
1192
1193 if (!devpriv->is_611x)
1194 return;
1195
1196 /* Check if there's a single sample stuck in the FIFO */
1197 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1198 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1199 data = dl & 0xffff;
1200 comedi_buf_write_samples(s, &data, 1);
1201 }
1202 }
1203
get_last_sample_6143(struct comedi_device * dev)1204 static void get_last_sample_6143(struct comedi_device *dev)
1205 {
1206 struct ni_private *devpriv = dev->private;
1207 struct comedi_subdevice *s = dev->read_subdev;
1208 unsigned short data;
1209 unsigned int dl;
1210
1211 if (!devpriv->is_6143)
1212 return;
1213
1214 /* Check if there's a single sample stuck in the FIFO */
1215 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1216 /* Get stranded sample into FIFO */
1217 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1218 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1219
1220 /* This may get the hi/lo data in the wrong order */
1221 data = (dl >> 16) & 0xffff;
1222 comedi_buf_write_samples(s, &data, 1);
1223 }
1224 }
1225
shutdown_ai_command(struct comedi_device * dev)1226 static void shutdown_ai_command(struct comedi_device *dev)
1227 {
1228 struct comedi_subdevice *s = dev->read_subdev;
1229
1230 #ifdef PCIDMA
1231 ni_ai_drain_dma(dev);
1232 #endif
1233 ni_handle_fifo_dregs(dev);
1234 get_last_sample_611x(dev);
1235 get_last_sample_6143(dev);
1236
1237 s->async->events |= COMEDI_CB_EOA;
1238 }
1239
ni_handle_eos(struct comedi_device * dev,struct comedi_subdevice * s)1240 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1241 {
1242 struct ni_private *devpriv = dev->private;
1243
1244 if (devpriv->aimode == AIMODE_SCAN) {
1245 #ifdef PCIDMA
1246 static const int timeout = 10;
1247 int i;
1248
1249 for (i = 0; i < timeout; i++) {
1250 ni_sync_ai_dma(dev);
1251 if ((s->async->events & COMEDI_CB_EOS))
1252 break;
1253 udelay(1);
1254 }
1255 #else
1256 ni_handle_fifo_dregs(dev);
1257 s->async->events |= COMEDI_CB_EOS;
1258 #endif
1259 }
1260 /* handle special case of single scan */
1261 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1262 shutdown_ai_command(dev);
1263 }
1264
handle_gpct_interrupt(struct comedi_device * dev,unsigned short counter_index)1265 static void handle_gpct_interrupt(struct comedi_device *dev,
1266 unsigned short counter_index)
1267 {
1268 #ifdef PCIDMA
1269 struct ni_private *devpriv = dev->private;
1270 struct comedi_subdevice *s;
1271
1272 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1273
1274 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1275 s);
1276 comedi_handle_events(dev, s);
1277 #endif
1278 }
1279
ack_a_interrupt(struct comedi_device * dev,unsigned short a_status)1280 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1281 {
1282 unsigned short ack = 0;
1283
1284 if (a_status & NISTC_AI_STATUS1_SC_TC)
1285 ack |= NISTC_INTA_ACK_AI_SC_TC;
1286 if (a_status & NISTC_AI_STATUS1_START1)
1287 ack |= NISTC_INTA_ACK_AI_START1;
1288 if (a_status & NISTC_AI_STATUS1_START)
1289 ack |= NISTC_INTA_ACK_AI_START;
1290 if (a_status & NISTC_AI_STATUS1_STOP)
1291 ack |= NISTC_INTA_ACK_AI_STOP;
1292 if (a_status & NISTC_AI_STATUS1_OVER)
1293 ack |= NISTC_INTA_ACK_AI_ERR;
1294 if (ack)
1295 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1296 }
1297
handle_a_interrupt(struct comedi_device * dev,struct comedi_subdevice * s,unsigned short status)1298 static void handle_a_interrupt(struct comedi_device *dev,
1299 struct comedi_subdevice *s,
1300 unsigned short status)
1301 {
1302 struct comedi_cmd *cmd = &s->async->cmd;
1303
1304 /* test for all uncommon interrupt events at the same time */
1305 if (status & (NISTC_AI_STATUS1_ERR |
1306 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1307 if (status == 0xffff) {
1308 dev_err(dev->class_dev, "Card removed?\n");
1309 /*
1310 * We probably aren't even running a command now,
1311 * so it's a good idea to be careful.
1312 */
1313 if (comedi_is_subdevice_running(s))
1314 s->async->events |= COMEDI_CB_ERROR;
1315 return;
1316 }
1317 if (status & NISTC_AI_STATUS1_ERR) {
1318 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1319 status);
1320
1321 shutdown_ai_command(dev);
1322
1323 s->async->events |= COMEDI_CB_ERROR;
1324 if (status & NISTC_AI_STATUS1_OVER)
1325 s->async->events |= COMEDI_CB_OVERFLOW;
1326 return;
1327 }
1328 if (status & NISTC_AI_STATUS1_SC_TC) {
1329 if (cmd->stop_src == TRIG_COUNT)
1330 shutdown_ai_command(dev);
1331 }
1332 }
1333 #ifndef PCIDMA
1334 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1335 int i;
1336 static const int timeout = 10;
1337 /*
1338 * PCMCIA cards (at least 6036) seem to stop producing
1339 * interrupts if we fail to get the fifo less than half
1340 * full, so loop to be sure.
1341 */
1342 for (i = 0; i < timeout; ++i) {
1343 ni_handle_fifo_half_full(dev);
1344 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1345 NISTC_AI_STATUS1_FIFO_HF) == 0)
1346 break;
1347 }
1348 }
1349 #endif /* !PCIDMA */
1350
1351 if (status & NISTC_AI_STATUS1_STOP)
1352 ni_handle_eos(dev, s);
1353 }
1354
ack_b_interrupt(struct comedi_device * dev,unsigned short b_status)1355 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1356 {
1357 unsigned short ack = 0;
1358
1359 if (b_status & NISTC_AO_STATUS1_BC_TC)
1360 ack |= NISTC_INTB_ACK_AO_BC_TC;
1361 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1362 ack |= NISTC_INTB_ACK_AO_ERR;
1363 if (b_status & NISTC_AO_STATUS1_START)
1364 ack |= NISTC_INTB_ACK_AO_START;
1365 if (b_status & NISTC_AO_STATUS1_START1)
1366 ack |= NISTC_INTB_ACK_AO_START1;
1367 if (b_status & NISTC_AO_STATUS1_UC_TC)
1368 ack |= NISTC_INTB_ACK_AO_UC_TC;
1369 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1370 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1371 if (b_status & NISTC_AO_STATUS1_UPDATE)
1372 ack |= NISTC_INTB_ACK_AO_UPDATE;
1373 if (ack)
1374 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1375 }
1376
handle_b_interrupt(struct comedi_device * dev,struct comedi_subdevice * s,unsigned short b_status)1377 static void handle_b_interrupt(struct comedi_device *dev,
1378 struct comedi_subdevice *s,
1379 unsigned short b_status)
1380 {
1381 if (b_status == 0xffff)
1382 return;
1383 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1384 dev_err(dev->class_dev,
1385 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1386 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1387 s->async->events |= COMEDI_CB_OVERFLOW;
1388 }
1389
1390 if (s->async->cmd.stop_src != TRIG_NONE &&
1391 b_status & NISTC_AO_STATUS1_BC_TC)
1392 s->async->events |= COMEDI_CB_EOA;
1393
1394 #ifndef PCIDMA
1395 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1396 int ret;
1397
1398 ret = ni_ao_fifo_half_empty(dev, s);
1399 if (!ret) {
1400 dev_err(dev->class_dev, "AO buffer underrun\n");
1401 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1402 NISTC_INTB_ENA_AO_FIFO |
1403 NISTC_INTB_ENA_AO_ERR, 0);
1404 s->async->events |= COMEDI_CB_OVERFLOW;
1405 }
1406 }
1407 #endif
1408 }
1409
ni_ai_munge(struct comedi_device * dev,struct comedi_subdevice * s,void * data,unsigned int num_bytes,unsigned int chan_index)1410 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1411 void *data, unsigned int num_bytes,
1412 unsigned int chan_index)
1413 {
1414 struct ni_private *devpriv = dev->private;
1415 struct comedi_async *async = s->async;
1416 struct comedi_cmd *cmd = &async->cmd;
1417 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1418 unsigned short *array = data;
1419 unsigned int *larray = data;
1420 unsigned int i;
1421 #ifdef PCIDMA
1422 __le16 *barray = data;
1423 __le32 *blarray = data;
1424 #endif
1425
1426 for (i = 0; i < nsamples; i++) {
1427 #ifdef PCIDMA
1428 if (s->subdev_flags & SDF_LSAMPL)
1429 larray[i] = le32_to_cpu(blarray[i]);
1430 else
1431 array[i] = le16_to_cpu(barray[i]);
1432 #endif
1433 if (s->subdev_flags & SDF_LSAMPL)
1434 larray[i] += devpriv->ai_offset[chan_index];
1435 else
1436 array[i] += devpriv->ai_offset[chan_index];
1437 chan_index++;
1438 chan_index %= cmd->chanlist_len;
1439 }
1440 }
1441
1442 #ifdef PCIDMA
1443
ni_ai_setup_MITE_dma(struct comedi_device * dev)1444 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1445 {
1446 struct ni_private *devpriv = dev->private;
1447 struct comedi_subdevice *s = dev->read_subdev;
1448 int retval;
1449 unsigned long flags;
1450
1451 retval = ni_request_ai_mite_channel(dev);
1452 if (retval)
1453 return retval;
1454
1455 /* write alloc the entire buffer */
1456 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1457
1458 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1459 if (!devpriv->ai_mite_chan) {
1460 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1461 return -EIO;
1462 }
1463
1464 if (devpriv->is_611x || devpriv->is_6143)
1465 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1466 else if (devpriv->is_628x)
1467 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1468 else
1469 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1470
1471 /*start the MITE */
1472 mite_dma_arm(devpriv->ai_mite_chan);
1473 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1474
1475 return 0;
1476 }
1477
ni_ao_setup_MITE_dma(struct comedi_device * dev)1478 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1479 {
1480 struct ni_private *devpriv = dev->private;
1481 struct comedi_subdevice *s = dev->write_subdev;
1482 int retval;
1483 unsigned long flags;
1484
1485 retval = ni_request_ao_mite_channel(dev);
1486 if (retval)
1487 return retval;
1488
1489 /* read alloc the entire buffer */
1490 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1491
1492 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1493 if (devpriv->ao_mite_chan) {
1494 if (devpriv->is_611x || devpriv->is_6713) {
1495 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1496 } else {
1497 /*
1498 * Doing 32 instead of 16 bit wide transfers from
1499 * memory makes the mite do 32 bit pci transfers,
1500 * doubling pci bandwidth.
1501 */
1502 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1503 }
1504 mite_dma_arm(devpriv->ao_mite_chan);
1505 } else {
1506 retval = -EIO;
1507 }
1508 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1509
1510 return retval;
1511 }
1512
1513 #endif /* PCIDMA */
1514
1515 /*
1516 * used for both cancel ioctl and board initialization
1517 *
1518 * this is pretty harsh for a cancel, but it works...
1519 */
ni_ai_reset(struct comedi_device * dev,struct comedi_subdevice * s)1520 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1521 {
1522 struct ni_private *devpriv = dev->private;
1523 unsigned int ai_personal;
1524 unsigned int ai_out_ctrl;
1525
1526 ni_release_ai_mite_channel(dev);
1527 /* ai configuration */
1528 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1529 NISTC_RESET_REG);
1530
1531 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1532
1533 ni_clear_ai_fifo(dev);
1534
1535 if (!devpriv->is_6143)
1536 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1537
1538 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1539 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1540 NISTC_AI_MODE1_RSVD
1541 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1542 NISTC_AI_MODE1_REG);
1543 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1544 /* generate FIFO interrupts on non-empty */
1545 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1546 NISTC_AI_MODE3_REG);
1547
1548 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1549 NISTC_AI_PERSONAL_SOC_POLARITY |
1550 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1551 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1552 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1553 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1554 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1555 if (devpriv->is_611x) {
1556 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1557 } else if (devpriv->is_6143) {
1558 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1559 } else {
1560 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1561 if (devpriv->is_622x)
1562 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1563 else
1564 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1565 }
1566 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1567 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1568
1569 /* the following registers should not be changed, because there
1570 * are no backup registers in devpriv. If you want to change
1571 * any of these, add a backup register and other appropriate code:
1572 * NISTC_AI_MODE1_REG
1573 * NISTC_AI_MODE3_REG
1574 * NISTC_AI_PERSONAL_REG
1575 * NISTC_AI_OUT_CTRL_REG
1576 */
1577
1578 /* clear interrupts */
1579 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1580
1581 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1582
1583 return 0;
1584 }
1585
ni_ai_poll(struct comedi_device * dev,struct comedi_subdevice * s)1586 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1587 {
1588 unsigned long flags;
1589 int count;
1590
1591 /* lock to avoid race with interrupt handler */
1592 spin_lock_irqsave(&dev->spinlock, flags);
1593 #ifndef PCIDMA
1594 ni_handle_fifo_dregs(dev);
1595 #else
1596 ni_sync_ai_dma(dev);
1597 #endif
1598 count = comedi_buf_n_bytes_ready(s);
1599 spin_unlock_irqrestore(&dev->spinlock, flags);
1600
1601 return count;
1602 }
1603
ni_prime_channelgain_list(struct comedi_device * dev)1604 static void ni_prime_channelgain_list(struct comedi_device *dev)
1605 {
1606 int i;
1607
1608 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1609 for (i = 0; i < NI_TIMEOUT; ++i) {
1610 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1611 NISTC_AI_STATUS1_FIFO_E)) {
1612 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1613 return;
1614 }
1615 udelay(1);
1616 }
1617 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1618 }
1619
ni_m_series_load_channelgain_list(struct comedi_device * dev,unsigned int n_chan,unsigned int * list)1620 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1621 unsigned int n_chan,
1622 unsigned int *list)
1623 {
1624 const struct ni_board_struct *board = dev->board_ptr;
1625 struct ni_private *devpriv = dev->private;
1626 unsigned int chan, range, aref;
1627 unsigned int i;
1628 unsigned int dither;
1629 unsigned int range_code;
1630
1631 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1632
1633 if ((list[0] & CR_ALT_SOURCE)) {
1634 unsigned int bypass_bits;
1635
1636 chan = CR_CHAN(list[0]);
1637 range = CR_RANGE(list[0]);
1638 range_code = ni_gainlkup[board->gainlkup][range];
1639 dither = (list[0] & CR_ALT_FILTER) != 0;
1640 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1641 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1642 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1643 devpriv->ai_calib_source;
1644 if (dither)
1645 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1646 /* don't use 2's complement encoding */
1647 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1648 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1649 } else {
1650 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1651 }
1652 for (i = 0; i < n_chan; i++) {
1653 unsigned int config_bits = 0;
1654
1655 chan = CR_CHAN(list[i]);
1656 aref = CR_AREF(list[i]);
1657 range = CR_RANGE(list[i]);
1658 dither = (list[i] & CR_ALT_FILTER) != 0;
1659
1660 range_code = ni_gainlkup[board->gainlkup][range];
1661 devpriv->ai_offset[i] = 0;
1662 switch (aref) {
1663 case AREF_DIFF:
1664 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1665 break;
1666 case AREF_COMMON:
1667 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1668 break;
1669 case AREF_GROUND:
1670 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1671 break;
1672 case AREF_OTHER:
1673 break;
1674 }
1675 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1676 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1677 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1678 if (i == n_chan - 1)
1679 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1680 if (dither)
1681 config_bits |= NI_M_AI_CFG_DITHER;
1682 /* don't use 2's complement encoding */
1683 config_bits |= NI_M_AI_CFG_POLARITY;
1684 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1685 }
1686 ni_prime_channelgain_list(dev);
1687 }
1688
1689 /*
1690 * Notes on the 6110 and 6111:
1691 * These boards a slightly different than the rest of the series, since
1692 * they have multiple A/D converters.
1693 * From the driver side, the configuration memory is a
1694 * little different.
1695 * Configuration Memory Low:
1696 * bits 15-9: same
1697 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1698 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1699 * 1001 gain=0.1 (+/- 50)
1700 * 1010 0.2
1701 * 1011 0.1
1702 * 0001 1
1703 * 0010 2
1704 * 0011 5
1705 * 0100 10
1706 * 0101 20
1707 * 0110 50
1708 * Configuration Memory High:
1709 * bits 12-14: Channel Type
1710 * 001 for differential
1711 * 000 for calibration
1712 * bit 11: coupling (this is not currently handled)
1713 * 1 AC coupling
1714 * 0 DC coupling
1715 * bits 0-2: channel
1716 * valid channels are 0-3
1717 */
ni_load_channelgain_list(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int n_chan,unsigned int * list)1718 static void ni_load_channelgain_list(struct comedi_device *dev,
1719 struct comedi_subdevice *s,
1720 unsigned int n_chan, unsigned int *list)
1721 {
1722 const struct ni_board_struct *board = dev->board_ptr;
1723 struct ni_private *devpriv = dev->private;
1724 unsigned int offset = (s->maxdata + 1) >> 1;
1725 unsigned int chan, range, aref;
1726 unsigned int i;
1727 unsigned int hi, lo;
1728 unsigned int dither;
1729
1730 if (devpriv->is_m_series) {
1731 ni_m_series_load_channelgain_list(dev, n_chan, list);
1732 return;
1733 }
1734 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1735 if (devpriv->changain_state &&
1736 devpriv->changain_spec == list[0]) {
1737 /* ready to go. */
1738 return;
1739 }
1740 devpriv->changain_state = 1;
1741 devpriv->changain_spec = list[0];
1742 } else {
1743 devpriv->changain_state = 0;
1744 }
1745
1746 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1747
1748 /* Set up Calibration mode if required */
1749 if (devpriv->is_6143) {
1750 if ((list[0] & CR_ALT_SOURCE) &&
1751 !devpriv->ai_calib_source_enabled) {
1752 /* Strobe Relay enable bit */
1753 ni_writew(dev, devpriv->ai_calib_source |
1754 NI6143_CALIB_CHAN_RELAY_ON,
1755 NI6143_CALIB_CHAN_REG);
1756 ni_writew(dev, devpriv->ai_calib_source,
1757 NI6143_CALIB_CHAN_REG);
1758 devpriv->ai_calib_source_enabled = 1;
1759 /* Allow relays to change */
1760 msleep_interruptible(100);
1761 } else if (!(list[0] & CR_ALT_SOURCE) &&
1762 devpriv->ai_calib_source_enabled) {
1763 /* Strobe Relay disable bit */
1764 ni_writew(dev, devpriv->ai_calib_source |
1765 NI6143_CALIB_CHAN_RELAY_OFF,
1766 NI6143_CALIB_CHAN_REG);
1767 ni_writew(dev, devpriv->ai_calib_source,
1768 NI6143_CALIB_CHAN_REG);
1769 devpriv->ai_calib_source_enabled = 0;
1770 /* Allow relays to change */
1771 msleep_interruptible(100);
1772 }
1773 }
1774
1775 for (i = 0; i < n_chan; i++) {
1776 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1777 chan = devpriv->ai_calib_source;
1778 else
1779 chan = CR_CHAN(list[i]);
1780 aref = CR_AREF(list[i]);
1781 range = CR_RANGE(list[i]);
1782 dither = (list[i] & CR_ALT_FILTER) != 0;
1783
1784 /* fix the external/internal range differences */
1785 range = ni_gainlkup[board->gainlkup][range];
1786 if (devpriv->is_611x)
1787 devpriv->ai_offset[i] = offset;
1788 else
1789 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1790
1791 hi = 0;
1792 if ((list[i] & CR_ALT_SOURCE)) {
1793 if (devpriv->is_611x)
1794 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1795 NI611X_CALIB_CHAN_SEL_REG);
1796 } else {
1797 if (devpriv->is_611x)
1798 aref = AREF_DIFF;
1799 else if (devpriv->is_6143)
1800 aref = AREF_OTHER;
1801 switch (aref) {
1802 case AREF_DIFF:
1803 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1804 break;
1805 case AREF_COMMON:
1806 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1807 break;
1808 case AREF_GROUND:
1809 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1810 break;
1811 case AREF_OTHER:
1812 break;
1813 }
1814 }
1815 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1816
1817 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1818
1819 if (!devpriv->is_6143) {
1820 lo = NI_E_AI_CFG_LO_GAIN(range);
1821
1822 if (i == n_chan - 1)
1823 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1824 if (dither)
1825 lo |= NI_E_AI_CFG_LO_DITHER;
1826
1827 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1828 }
1829 }
1830
1831 /* prime the channel/gain list */
1832 if (!devpriv->is_611x && !devpriv->is_6143)
1833 ni_prime_channelgain_list(dev);
1834 }
1835
ni_ai_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)1836 static int ni_ai_insn_read(struct comedi_device *dev,
1837 struct comedi_subdevice *s,
1838 struct comedi_insn *insn,
1839 unsigned int *data)
1840 {
1841 struct ni_private *devpriv = dev->private;
1842 unsigned int mask = s->maxdata;
1843 int i, n;
1844 unsigned int signbits;
1845 unsigned int d;
1846
1847 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1848
1849 ni_clear_ai_fifo(dev);
1850
1851 signbits = devpriv->ai_offset[0];
1852 if (devpriv->is_611x) {
1853 for (n = 0; n < num_adc_stages_611x; n++) {
1854 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1855 NISTC_AI_CMD1_REG);
1856 udelay(1);
1857 }
1858 for (n = 0; n < insn->n; n++) {
1859 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1860 NISTC_AI_CMD1_REG);
1861 /* The 611x has screwy 32-bit FIFOs. */
1862 d = 0;
1863 for (i = 0; i < NI_TIMEOUT; i++) {
1864 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1865 d = ni_readl(dev,
1866 NI611X_AI_FIFO_DATA_REG);
1867 d >>= 16;
1868 d &= 0xffff;
1869 break;
1870 }
1871 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1872 NISTC_AI_STATUS1_FIFO_E)) {
1873 d = ni_readl(dev,
1874 NI611X_AI_FIFO_DATA_REG);
1875 d &= 0xffff;
1876 break;
1877 }
1878 }
1879 if (i == NI_TIMEOUT) {
1880 dev_err(dev->class_dev, "timeout\n");
1881 return -ETIME;
1882 }
1883 d += signbits;
1884 data[n] = d & 0xffff;
1885 }
1886 } else if (devpriv->is_6143) {
1887 for (n = 0; n < insn->n; n++) {
1888 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1889 NISTC_AI_CMD1_REG);
1890
1891 /*
1892 * The 6143 has 32-bit FIFOs. You need to strobe a
1893 * bit to move a single 16bit stranded sample into
1894 * the FIFO.
1895 */
1896 d = 0;
1897 for (i = 0; i < NI_TIMEOUT; i++) {
1898 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1899 0x01) {
1900 /* Get stranded sample into FIFO */
1901 ni_writel(dev, 0x01,
1902 NI6143_AI_FIFO_CTRL_REG);
1903 d = ni_readl(dev,
1904 NI6143_AI_FIFO_DATA_REG);
1905 break;
1906 }
1907 }
1908 if (i == NI_TIMEOUT) {
1909 dev_err(dev->class_dev, "timeout\n");
1910 return -ETIME;
1911 }
1912 data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1913 }
1914 } else {
1915 for (n = 0; n < insn->n; n++) {
1916 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1917 NISTC_AI_CMD1_REG);
1918 for (i = 0; i < NI_TIMEOUT; i++) {
1919 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1920 NISTC_AI_STATUS1_FIFO_E))
1921 break;
1922 }
1923 if (i == NI_TIMEOUT) {
1924 dev_err(dev->class_dev, "timeout\n");
1925 return -ETIME;
1926 }
1927 if (devpriv->is_m_series) {
1928 d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1929 d &= mask;
1930 data[n] = d;
1931 } else {
1932 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1933 d += signbits;
1934 data[n] = d & 0xffff;
1935 }
1936 }
1937 }
1938 return insn->n;
1939 }
1940
ni_ns_to_timer(const struct comedi_device * dev,unsigned int nanosec,unsigned int flags)1941 static int ni_ns_to_timer(const struct comedi_device *dev,
1942 unsigned int nanosec, unsigned int flags)
1943 {
1944 struct ni_private *devpriv = dev->private;
1945 int divider;
1946
1947 switch (flags & CMDF_ROUND_MASK) {
1948 case CMDF_ROUND_NEAREST:
1949 default:
1950 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1951 break;
1952 case CMDF_ROUND_DOWN:
1953 divider = (nanosec) / devpriv->clock_ns;
1954 break;
1955 case CMDF_ROUND_UP:
1956 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1957 break;
1958 }
1959 return divider - 1;
1960 }
1961
ni_timer_to_ns(const struct comedi_device * dev,int timer)1962 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1963 {
1964 struct ni_private *devpriv = dev->private;
1965
1966 return devpriv->clock_ns * (timer + 1);
1967 }
1968
ni_cmd_set_mite_transfer(struct mite_ring * ring,struct comedi_subdevice * sdev,const struct comedi_cmd * cmd,unsigned int max_count)1969 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1970 struct comedi_subdevice *sdev,
1971 const struct comedi_cmd *cmd,
1972 unsigned int max_count)
1973 {
1974 #ifdef PCIDMA
1975 unsigned int nbytes = max_count;
1976
1977 if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1978 nbytes = cmd->stop_arg;
1979 nbytes *= comedi_bytes_per_scan(sdev);
1980
1981 if (nbytes > sdev->async->prealloc_bufsz) {
1982 if (cmd->stop_arg > 0)
1983 dev_err(sdev->device->class_dev,
1984 "%s: tried exact data transfer limits greater than buffer size\n",
1985 __func__);
1986
1987 /*
1988 * we can only transfer up to the size of the buffer. In this
1989 * case, the user is expected to continue to write into the
1990 * comedi buffer (already implemented as a ring buffer).
1991 */
1992 nbytes = sdev->async->prealloc_bufsz;
1993 }
1994
1995 mite_init_ring_descriptors(ring, sdev, nbytes);
1996 #else
1997 dev_err(sdev->device->class_dev,
1998 "%s: exact data transfer limits not implemented yet without DMA\n",
1999 __func__);
2000 #endif
2001 }
2002
ni_min_ai_scan_period_ns(struct comedi_device * dev,unsigned int num_channels)2003 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
2004 unsigned int num_channels)
2005 {
2006 const struct ni_board_struct *board = dev->board_ptr;
2007 struct ni_private *devpriv = dev->private;
2008
2009 /* simultaneously-sampled inputs */
2010 if (devpriv->is_611x || devpriv->is_6143)
2011 return board->ai_speed;
2012
2013 /* multiplexed inputs */
2014 return board->ai_speed * num_channels;
2015 }
2016
ni_ai_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)2017 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2018 struct comedi_cmd *cmd)
2019 {
2020 const struct ni_board_struct *board = dev->board_ptr;
2021 struct ni_private *devpriv = dev->private;
2022 int err = 0;
2023 unsigned int sources;
2024
2025 /* Step 1 : check if triggers are trivially valid */
2026
2027 err |= comedi_check_trigger_src(&cmd->start_src,
2028 TRIG_NOW | TRIG_INT | TRIG_EXT);
2029 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2030 TRIG_TIMER | TRIG_EXT);
2031
2032 sources = TRIG_TIMER | TRIG_EXT;
2033 if (devpriv->is_611x || devpriv->is_6143)
2034 sources |= TRIG_NOW;
2035 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2036
2037 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2038 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2039
2040 if (err)
2041 return 1;
2042
2043 /* Step 2a : make sure trigger sources are unique */
2044
2045 err |= comedi_check_trigger_is_unique(cmd->start_src);
2046 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2047 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2048 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2049
2050 /* Step 2b : and mutually compatible */
2051
2052 if (err)
2053 return 2;
2054
2055 /* Step 3: check if arguments are trivially valid */
2056
2057 switch (cmd->start_src) {
2058 case TRIG_NOW:
2059 case TRIG_INT:
2060 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2061 break;
2062 case TRIG_EXT:
2063 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
2064 NI_AI_StartTrigger,
2065 &devpriv->routing_tables, 1);
2066 break;
2067 }
2068
2069 if (cmd->scan_begin_src == TRIG_TIMER) {
2070 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2071 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2072 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2073 devpriv->clock_ns *
2074 0xffffff);
2075 } else if (cmd->scan_begin_src == TRIG_EXT) {
2076 /* external trigger */
2077 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->scan_begin_arg),
2078 NI_AI_SampleClock,
2079 &devpriv->routing_tables, 1);
2080 } else { /* TRIG_OTHER */
2081 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2082 }
2083
2084 if (cmd->convert_src == TRIG_TIMER) {
2085 if (devpriv->is_611x || devpriv->is_6143) {
2086 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2087 0);
2088 } else {
2089 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2090 board->ai_speed);
2091 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2092 devpriv->clock_ns *
2093 0xffff);
2094 }
2095 } else if (cmd->convert_src == TRIG_EXT) {
2096 /* external trigger */
2097 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->convert_arg),
2098 NI_AI_ConvertClock,
2099 &devpriv->routing_tables, 1);
2100 } else if (cmd->convert_src == TRIG_NOW) {
2101 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2102 }
2103
2104 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2105 cmd->chanlist_len);
2106
2107 if (cmd->stop_src == TRIG_COUNT) {
2108 unsigned int max_count = 0x01000000;
2109
2110 if (devpriv->is_611x)
2111 max_count -= num_adc_stages_611x;
2112 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2113 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2114 } else {
2115 /* TRIG_NONE */
2116 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2117 }
2118
2119 if (err)
2120 return 3;
2121
2122 /* step 4: fix up any arguments */
2123
2124 if (cmd->scan_begin_src == TRIG_TIMER) {
2125 unsigned int tmp = cmd->scan_begin_arg;
2126
2127 cmd->scan_begin_arg =
2128 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2129 cmd->scan_begin_arg,
2130 cmd->flags));
2131 if (tmp != cmd->scan_begin_arg)
2132 err++;
2133 }
2134 if (cmd->convert_src == TRIG_TIMER) {
2135 if (!devpriv->is_611x && !devpriv->is_6143) {
2136 unsigned int tmp = cmd->convert_arg;
2137
2138 cmd->convert_arg =
2139 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2140 cmd->convert_arg,
2141 cmd->flags));
2142 if (tmp != cmd->convert_arg)
2143 err++;
2144 if (cmd->scan_begin_src == TRIG_TIMER &&
2145 cmd->scan_begin_arg <
2146 cmd->convert_arg * cmd->scan_end_arg) {
2147 cmd->scan_begin_arg =
2148 cmd->convert_arg * cmd->scan_end_arg;
2149 err++;
2150 }
2151 }
2152 }
2153
2154 if (err)
2155 return 4;
2156
2157 return 0;
2158 }
2159
ni_ai_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)2160 static int ni_ai_inttrig(struct comedi_device *dev,
2161 struct comedi_subdevice *s,
2162 unsigned int trig_num)
2163 {
2164 struct ni_private *devpriv = dev->private;
2165 struct comedi_cmd *cmd = &s->async->cmd;
2166
2167 if (trig_num != cmd->start_arg)
2168 return -EINVAL;
2169
2170 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2171 NISTC_AI_CMD2_REG);
2172 s->async->inttrig = NULL;
2173
2174 return 1;
2175 }
2176
ni_ai_cmd(struct comedi_device * dev,struct comedi_subdevice * s)2177 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2178 {
2179 struct ni_private *devpriv = dev->private;
2180 const struct comedi_cmd *cmd = &s->async->cmd;
2181 int timer;
2182 int mode1 = 0; /* mode1 is needed for both stop and convert */
2183 int mode2 = 0;
2184 int start_stop_select = 0;
2185 unsigned int stop_count;
2186 int interrupt_a_enable = 0;
2187 unsigned int ai_trig;
2188
2189 if (dev->irq == 0) {
2190 dev_err(dev->class_dev, "cannot run command without an irq\n");
2191 return -EIO;
2192 }
2193 ni_clear_ai_fifo(dev);
2194
2195 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2196
2197 /* start configuration */
2198 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2199
2200 /*
2201 * Disable analog triggering for now, since it interferes
2202 * with the use of pfi0.
2203 */
2204 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2205 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2206
2207 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2208 switch (cmd->start_src) {
2209 case TRIG_INT:
2210 case TRIG_NOW:
2211 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2212 NISTC_AI_TRIG_START1_SEL(0);
2213 break;
2214 case TRIG_EXT:
2215 ai_trig |= NISTC_AI_TRIG_START1_SEL(
2216 ni_get_reg_value_roffs(
2217 CR_CHAN(cmd->start_arg),
2218 NI_AI_StartTrigger,
2219 &devpriv->routing_tables, 1));
2220
2221 if (cmd->start_arg & CR_INVERT)
2222 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2223 if (cmd->start_arg & CR_EDGE)
2224 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2225 break;
2226 }
2227 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2228
2229 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2230 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2231 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2232 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2233
2234 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2235 /* logic low */
2236 start_stop_select |= NISTC_AI_STOP_POLARITY |
2237 NISTC_AI_STOP_SEL(31) |
2238 NISTC_AI_STOP_SYNC;
2239 } else {
2240 /* ai configuration memory */
2241 start_stop_select |= NISTC_AI_STOP_SEL(19);
2242 }
2243 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2244
2245 devpriv->ai_cmd2 = 0;
2246 switch (cmd->stop_src) {
2247 case TRIG_COUNT:
2248 stop_count = cmd->stop_arg - 1;
2249
2250 if (devpriv->is_611x) {
2251 /* have to take 3 stage adc pipeline into account */
2252 stop_count += num_adc_stages_611x;
2253 }
2254 /* stage number of scans */
2255 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2256
2257 mode1 |= NISTC_AI_MODE1_START_STOP |
2258 NISTC_AI_MODE1_RSVD |
2259 NISTC_AI_MODE1_TRIGGER_ONCE;
2260 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2261 /* load SC (Scan Count) */
2262 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2263
2264 if (stop_count == 0) {
2265 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2266 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2267 /*
2268 * This is required to get the last sample for
2269 * chanlist_len > 1, not sure why.
2270 */
2271 if (cmd->chanlist_len > 1)
2272 start_stop_select |= NISTC_AI_STOP_POLARITY |
2273 NISTC_AI_STOP_EDGE;
2274 }
2275 break;
2276 case TRIG_NONE:
2277 /* stage number of scans */
2278 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2279
2280 mode1 |= NISTC_AI_MODE1_START_STOP |
2281 NISTC_AI_MODE1_RSVD |
2282 NISTC_AI_MODE1_CONTINUOUS;
2283 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2284
2285 /* load SC (Scan Count) */
2286 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2287 break;
2288 }
2289
2290 switch (cmd->scan_begin_src) {
2291 case TRIG_TIMER:
2292 /*
2293 * stop bits for non 611x boards
2294 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2295 * NISTC_AI_MODE2_PRE_TRIGGER=0
2296 * NISTC_AI_START_STOP_REG:
2297 * NISTC_AI_START_POLARITY=0 (?) rising edge
2298 * NISTC_AI_START_EDGE=1 edge triggered
2299 * NISTC_AI_START_SYNC=1 (?)
2300 * NISTC_AI_START_SEL=0 SI_TC
2301 * NISTC_AI_STOP_POLARITY=0 rising edge
2302 * NISTC_AI_STOP_EDGE=0 level
2303 * NISTC_AI_STOP_SYNC=1
2304 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2305 */
2306 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2307 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2308
2309 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2310 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2311 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2312 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2313
2314 /* load SI */
2315 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2316 CMDF_ROUND_NEAREST);
2317 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2318 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2319 break;
2320 case TRIG_EXT:
2321 if (cmd->scan_begin_arg & CR_EDGE)
2322 start_stop_select |= NISTC_AI_START_EDGE;
2323 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2324 start_stop_select |= NISTC_AI_START_POLARITY;
2325 if (cmd->scan_begin_src != cmd->convert_src ||
2326 (cmd->scan_begin_arg & ~CR_EDGE) !=
2327 (cmd->convert_arg & ~CR_EDGE))
2328 start_stop_select |= NISTC_AI_START_SYNC;
2329
2330 start_stop_select |= NISTC_AI_START_SEL(
2331 ni_get_reg_value_roffs(
2332 CR_CHAN(cmd->scan_begin_arg),
2333 NI_AI_SampleClock,
2334 &devpriv->routing_tables, 1));
2335 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2336 break;
2337 }
2338
2339 switch (cmd->convert_src) {
2340 case TRIG_TIMER:
2341 case TRIG_NOW:
2342 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2343 timer = 1;
2344 else
2345 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2346 CMDF_ROUND_NEAREST);
2347 /* 0,0 does not work */
2348 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2349 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2350
2351 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2352 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2353 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2354
2355 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2356
2357 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2358 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2359 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2360 break;
2361 case TRIG_EXT:
2362 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(
2363 ni_get_reg_value_roffs(
2364 CR_CHAN(cmd->convert_arg),
2365 NI_AI_ConvertClock,
2366 &devpriv->routing_tables, 1));
2367 if ((cmd->convert_arg & CR_INVERT) == 0)
2368 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2369 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2370
2371 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2372 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2373 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2374
2375 break;
2376 }
2377
2378 if (dev->irq) {
2379 /* interrupt on FIFO, errors, SC_TC */
2380 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2381 NISTC_INTA_ENA_AI_SC_TC;
2382
2383 #ifndef PCIDMA
2384 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2385 #endif
2386
2387 if ((cmd->flags & CMDF_WAKE_EOS) ||
2388 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2389 /* wake on end-of-scan */
2390 devpriv->aimode = AIMODE_SCAN;
2391 } else {
2392 devpriv->aimode = AIMODE_HALF_FULL;
2393 }
2394
2395 switch (devpriv->aimode) {
2396 case AIMODE_HALF_FULL:
2397 /* FIFO interrupts and DMA requests on half-full */
2398 #ifdef PCIDMA
2399 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2400 NISTC_AI_MODE3_REG);
2401 #else
2402 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2403 NISTC_AI_MODE3_REG);
2404 #endif
2405 break;
2406 case AIMODE_SAMPLE:
2407 /* generate FIFO interrupts on non-empty */
2408 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2409 NISTC_AI_MODE3_REG);
2410 break;
2411 case AIMODE_SCAN:
2412 #ifdef PCIDMA
2413 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2414 NISTC_AI_MODE3_REG);
2415 #else
2416 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2417 NISTC_AI_MODE3_REG);
2418 #endif
2419 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2420 break;
2421 default:
2422 break;
2423 }
2424
2425 /* clear interrupts */
2426 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2427
2428 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2429 } else {
2430 /* interrupt on nothing */
2431 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2432
2433 /* XXX start polling if necessary */
2434 }
2435
2436 /* end configuration */
2437 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2438
2439 switch (cmd->scan_begin_src) {
2440 case TRIG_TIMER:
2441 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2442 NISTC_AI_CMD1_SI_ARM |
2443 NISTC_AI_CMD1_DIV_ARM |
2444 NISTC_AI_CMD1_SC_ARM,
2445 NISTC_AI_CMD1_REG);
2446 break;
2447 case TRIG_EXT:
2448 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2449 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2450 NISTC_AI_CMD1_DIV_ARM |
2451 NISTC_AI_CMD1_SC_ARM,
2452 NISTC_AI_CMD1_REG);
2453 break;
2454 }
2455
2456 #ifdef PCIDMA
2457 {
2458 int retval = ni_ai_setup_MITE_dma(dev);
2459
2460 if (retval)
2461 return retval;
2462 }
2463 #endif
2464
2465 if (cmd->start_src == TRIG_NOW) {
2466 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2467 devpriv->ai_cmd2,
2468 NISTC_AI_CMD2_REG);
2469 s->async->inttrig = NULL;
2470 } else if (cmd->start_src == TRIG_EXT) {
2471 s->async->inttrig = NULL;
2472 } else { /* TRIG_INT */
2473 s->async->inttrig = ni_ai_inttrig;
2474 }
2475
2476 return 0;
2477 }
2478
ni_ai_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)2479 static int ni_ai_insn_config(struct comedi_device *dev,
2480 struct comedi_subdevice *s,
2481 struct comedi_insn *insn, unsigned int *data)
2482 {
2483 const struct ni_board_struct *board = dev->board_ptr;
2484 struct ni_private *devpriv = dev->private;
2485
2486 if (insn->n < 1)
2487 return -EINVAL;
2488
2489 switch (data[0]) {
2490 case INSN_CONFIG_ALT_SOURCE:
2491 if (devpriv->is_m_series) {
2492 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2493 return -EINVAL;
2494 devpriv->ai_calib_source = data[1];
2495 } else if (devpriv->is_6143) {
2496 unsigned int calib_source;
2497
2498 calib_source = data[1] & 0xf;
2499
2500 devpriv->ai_calib_source = calib_source;
2501 ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2502 } else {
2503 unsigned int calib_source;
2504 unsigned int calib_source_adjust;
2505
2506 calib_source = data[1] & 0xf;
2507 calib_source_adjust = (data[1] >> 4) & 0xff;
2508
2509 if (calib_source >= 8)
2510 return -EINVAL;
2511 devpriv->ai_calib_source = calib_source;
2512 if (devpriv->is_611x) {
2513 ni_writeb(dev, calib_source_adjust,
2514 NI611X_CAL_GAIN_SEL_REG);
2515 }
2516 }
2517 return 2;
2518 case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2519 /* we don't care about actual channels */
2520 /* data[3] : chanlist_len */
2521 data[1] = ni_min_ai_scan_period_ns(dev, data[3]);
2522 if (devpriv->is_611x || devpriv->is_6143)
2523 data[2] = 0; /* simultaneous output */
2524 else
2525 data[2] = board->ai_speed;
2526 return 0;
2527 default:
2528 break;
2529 }
2530
2531 return -EINVAL;
2532 }
2533
ni_ao_munge(struct comedi_device * dev,struct comedi_subdevice * s,void * data,unsigned int num_bytes,unsigned int chan_index)2534 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2535 void *data, unsigned int num_bytes,
2536 unsigned int chan_index)
2537 {
2538 struct comedi_cmd *cmd = &s->async->cmd;
2539 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2540 unsigned short *array = data;
2541 unsigned int i;
2542 #ifdef PCIDMA
2543 __le16 buf, *barray = data;
2544 #endif
2545
2546 for (i = 0; i < nsamples; i++) {
2547 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2548 unsigned short val = array[i];
2549
2550 /*
2551 * Munge data from unsigned to two's complement for
2552 * bipolar ranges.
2553 */
2554 if (comedi_range_is_bipolar(s, range))
2555 val = comedi_offset_munge(s, val);
2556 #ifdef PCIDMA
2557 buf = cpu_to_le16(val);
2558 barray[i] = buf;
2559 #else
2560 array[i] = val;
2561 #endif
2562 chan_index++;
2563 chan_index %= cmd->chanlist_len;
2564 }
2565 }
2566
ni_m_series_ao_config_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int chanspec[],unsigned int n_chans,int timed)2567 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2568 struct comedi_subdevice *s,
2569 unsigned int chanspec[],
2570 unsigned int n_chans, int timed)
2571 {
2572 struct ni_private *devpriv = dev->private;
2573 unsigned int range;
2574 unsigned int chan;
2575 unsigned int conf;
2576 int i;
2577 int invert = 0;
2578
2579 if (timed) {
2580 for (i = 0; i < s->n_chan; ++i) {
2581 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2582 ni_writeb(dev, devpriv->ao_conf[i],
2583 NI_M_AO_CFG_BANK_REG(i));
2584 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2585 }
2586 }
2587 for (i = 0; i < n_chans; i++) {
2588 const struct comedi_krange *krange;
2589
2590 chan = CR_CHAN(chanspec[i]);
2591 range = CR_RANGE(chanspec[i]);
2592 krange = s->range_table->range + range;
2593 invert = 0;
2594 conf = 0;
2595 switch (krange->max - krange->min) {
2596 case 20000000:
2597 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2598 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2599 break;
2600 case 10000000:
2601 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2602 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2603 break;
2604 case 4000000:
2605 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2606 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2607 NI_M_AO_REF_ATTENUATION_REG(chan));
2608 break;
2609 case 2000000:
2610 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2611 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2612 NI_M_AO_REF_ATTENUATION_REG(chan));
2613 break;
2614 default:
2615 dev_err(dev->class_dev,
2616 "bug! unhandled ao reference voltage\n");
2617 break;
2618 }
2619 switch (krange->max + krange->min) {
2620 case 0:
2621 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2622 break;
2623 case 10000000:
2624 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2625 break;
2626 default:
2627 dev_err(dev->class_dev,
2628 "bug! unhandled ao offset voltage\n");
2629 break;
2630 }
2631 if (timed)
2632 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2633 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2634 devpriv->ao_conf[chan] = conf;
2635 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2636 }
2637 return invert;
2638 }
2639
ni_old_ao_config_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int chanspec[],unsigned int n_chans)2640 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2641 struct comedi_subdevice *s,
2642 unsigned int chanspec[],
2643 unsigned int n_chans)
2644 {
2645 struct ni_private *devpriv = dev->private;
2646 unsigned int range;
2647 unsigned int chan;
2648 unsigned int conf;
2649 int i;
2650 int invert = 0;
2651
2652 for (i = 0; i < n_chans; i++) {
2653 chan = CR_CHAN(chanspec[i]);
2654 range = CR_RANGE(chanspec[i]);
2655 conf = NI_E_AO_DACSEL(chan);
2656
2657 if (comedi_range_is_bipolar(s, range)) {
2658 conf |= NI_E_AO_CFG_BIP;
2659 invert = (s->maxdata + 1) >> 1;
2660 } else {
2661 invert = 0;
2662 }
2663 if (comedi_range_is_external(s, range))
2664 conf |= NI_E_AO_EXT_REF;
2665
2666 /* not all boards can deglitch, but this shouldn't hurt */
2667 if (chanspec[i] & CR_DEGLITCH)
2668 conf |= NI_E_AO_DEGLITCH;
2669
2670 /* analog reference */
2671 /* AREF_OTHER connects AO ground to AI ground, i think */
2672 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2673 conf |= NI_E_AO_GROUND_REF;
2674
2675 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2676 devpriv->ao_conf[chan] = conf;
2677 }
2678 return invert;
2679 }
2680
ni_ao_config_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int chanspec[],unsigned int n_chans,int timed)2681 static int ni_ao_config_chanlist(struct comedi_device *dev,
2682 struct comedi_subdevice *s,
2683 unsigned int chanspec[], unsigned int n_chans,
2684 int timed)
2685 {
2686 struct ni_private *devpriv = dev->private;
2687
2688 if (devpriv->is_m_series)
2689 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2690 timed);
2691 else
2692 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2693 }
2694
ni_ao_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)2695 static int ni_ao_insn_write(struct comedi_device *dev,
2696 struct comedi_subdevice *s,
2697 struct comedi_insn *insn,
2698 unsigned int *data)
2699 {
2700 struct ni_private *devpriv = dev->private;
2701 unsigned int chan = CR_CHAN(insn->chanspec);
2702 unsigned int range = CR_RANGE(insn->chanspec);
2703 int reg;
2704 int i;
2705
2706 if (devpriv->is_6xxx) {
2707 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2708
2709 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2710 } else if (devpriv->is_m_series) {
2711 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2712 } else {
2713 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2714 }
2715
2716 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2717
2718 for (i = 0; i < insn->n; i++) {
2719 unsigned int val = data[i];
2720
2721 s->readback[chan] = val;
2722
2723 if (devpriv->is_6xxx) {
2724 /*
2725 * 6xxx boards have bipolar outputs, munge the
2726 * unsigned comedi values to 2's complement
2727 */
2728 val = comedi_offset_munge(s, val);
2729
2730 ni_ao_win_outw(dev, val, reg);
2731 } else if (devpriv->is_m_series) {
2732 /*
2733 * M-series boards use offset binary values for
2734 * bipolar and uinpolar outputs
2735 */
2736 ni_writew(dev, val, reg);
2737 } else {
2738 /*
2739 * Non-M series boards need two's complement values
2740 * for bipolar ranges.
2741 */
2742 if (comedi_range_is_bipolar(s, range))
2743 val = comedi_offset_munge(s, val);
2744
2745 ni_writew(dev, val, reg);
2746 }
2747 }
2748
2749 return insn->n;
2750 }
2751
2752 /*
2753 * Arms the AO device in preparation for a trigger event.
2754 * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2755 * not used). As a part of this preparation, this function preloads the DAC
2756 * registers with the first values of the output stream. This ensures that the
2757 * first clock cycle after the trigger can be used for output.
2758 *
2759 * Note that this function _must_ happen after a user has written data to the
2760 * output buffers via either mmap or write(fileno,...).
2761 */
ni_ao_arm(struct comedi_device * dev,struct comedi_subdevice * s)2762 static int ni_ao_arm(struct comedi_device *dev,
2763 struct comedi_subdevice *s)
2764 {
2765 struct ni_private *devpriv = dev->private;
2766 int ret;
2767 int interrupt_b_bits;
2768 int i;
2769 static const int timeout = 1000;
2770
2771 /*
2772 * Prevent ao from doing things like trying to allocate the ao dma
2773 * channel multiple times.
2774 */
2775 if (!devpriv->ao_needs_arming) {
2776 dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2777 __func__);
2778 return -EINVAL;
2779 }
2780
2781 devpriv->ao_needs_arming = 0;
2782
2783 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2784 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2785 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2786 #ifdef PCIDMA
2787 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2788 if (devpriv->is_6xxx)
2789 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2790 ret = ni_ao_setup_MITE_dma(dev);
2791 if (ret)
2792 return ret;
2793 ret = ni_ao_wait_for_dma_load(dev);
2794 if (ret < 0)
2795 return ret;
2796 #else
2797 ret = ni_ao_prep_fifo(dev, s);
2798 if (ret == 0)
2799 return -EPIPE;
2800
2801 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2802 #endif
2803
2804 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2805 NISTC_AO_MODE3_REG);
2806 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2807 /* wait for DACs to be loaded */
2808 for (i = 0; i < timeout; i++) {
2809 udelay(1);
2810 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2811 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2812 break;
2813 }
2814 if (i == timeout) {
2815 dev_err(dev->class_dev,
2816 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2817 return -EIO;
2818 }
2819 /*
2820 * stc manual says we are need to clear error interrupt after
2821 * AO_TMRDACWRs_In_Progress_St clears
2822 */
2823 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2824
2825 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2826
2827 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2828 NISTC_AO_CMD1_UC_ARM |
2829 NISTC_AO_CMD1_BC_ARM |
2830 devpriv->ao_cmd1,
2831 NISTC_AO_CMD1_REG);
2832
2833 return 0;
2834 }
2835
ni_ao_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)2836 static int ni_ao_insn_config(struct comedi_device *dev,
2837 struct comedi_subdevice *s,
2838 struct comedi_insn *insn, unsigned int *data)
2839 {
2840 const struct ni_board_struct *board = dev->board_ptr;
2841 struct ni_private *devpriv = dev->private;
2842 unsigned int nbytes;
2843
2844 switch (data[0]) {
2845 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2846 switch (data[1]) {
2847 case COMEDI_OUTPUT:
2848 nbytes = comedi_samples_to_bytes(s,
2849 board->ao_fifo_depth);
2850 data[2] = 1 + nbytes;
2851 if (devpriv->mite)
2852 data[2] += devpriv->mite->fifo_size;
2853 break;
2854 case COMEDI_INPUT:
2855 data[2] = 0;
2856 break;
2857 default:
2858 return -EINVAL;
2859 }
2860 return 0;
2861 case INSN_CONFIG_ARM:
2862 return ni_ao_arm(dev, s);
2863 case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2864 /* we don't care about actual channels */
2865 /* data[3] : chanlist_len */
2866 data[1] = board->ao_speed * data[3];
2867 data[2] = 0;
2868 return 0;
2869 default:
2870 break;
2871 }
2872
2873 return -EINVAL;
2874 }
2875
ni_ao_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)2876 static int ni_ao_inttrig(struct comedi_device *dev,
2877 struct comedi_subdevice *s,
2878 unsigned int trig_num)
2879 {
2880 struct ni_private *devpriv = dev->private;
2881 struct comedi_cmd *cmd = &s->async->cmd;
2882 int ret;
2883
2884 /*
2885 * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2886 * For backwards compatibility, also allow trig_num == 0 when
2887 * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2888 * in that case, the internal trigger is being used as a pre-trigger
2889 * before the external trigger.
2890 */
2891 if (!(trig_num == cmd->start_arg ||
2892 (trig_num == 0 && cmd->start_src != TRIG_INT)))
2893 return -EINVAL;
2894
2895 /*
2896 * Null trig at beginning prevent ao start trigger from executing more
2897 * than once per command.
2898 */
2899 s->async->inttrig = NULL;
2900
2901 if (devpriv->ao_needs_arming) {
2902 /* only arm this device if it still needs arming */
2903 ret = ni_ao_arm(dev, s);
2904 if (ret)
2905 return ret;
2906 }
2907
2908 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2909 NISTC_AO_CMD2_REG);
2910
2911 return 0;
2912 }
2913
2914 /*
2915 * begin ni_ao_cmd.
2916 * Organized similar to NI-STC and MHDDK examples.
2917 * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2918 */
2919
ni_ao_cmd_personalize(struct comedi_device * dev,const struct comedi_cmd * cmd)2920 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2921 const struct comedi_cmd *cmd)
2922 {
2923 const struct ni_board_struct *board = dev->board_ptr;
2924 unsigned int bits;
2925
2926 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2927
2928 bits =
2929 /* fast CPU interface--only eseries */
2930 /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2931 NISTC_AO_PERSONAL_BC_SRC_SEL |
2932 0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2933 /*
2934 * FIXME: start setting following bit when appropriate. Need to
2935 * determine whether board is E4 or E1.
2936 * FROM MHHDK:
2937 * if board is E4 or E1
2938 * Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2939 * else
2940 * set it to 1
2941 */
2942 NISTC_AO_PERSONAL_UPDATE_PW |
2943 /* FIXME: when should we set following bit to zero? */
2944 NISTC_AO_PERSONAL_TMRDACWR_PW |
2945 (board->ao_fifo_depth ?
2946 NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2947 ;
2948 #if 0
2949 /*
2950 * FIXME:
2951 * add something like ".has_individual_dacs = 0" to ni_board_struct
2952 * since, as F Hess pointed out, not all in m series have singles. not
2953 * sure if e-series all have duals...
2954 */
2955
2956 /*
2957 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2958 * 6281, verified with bus analyzer.
2959 */
2960 if (devpriv->is_m_series)
2961 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2962 #endif
2963 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2964
2965 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2966 }
2967
ni_ao_cmd_set_trigger(struct comedi_device * dev,const struct comedi_cmd * cmd)2968 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2969 const struct comedi_cmd *cmd)
2970 {
2971 struct ni_private *devpriv = dev->private;
2972 unsigned int trigsel;
2973
2974 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2975
2976 /* sync */
2977 if (cmd->stop_src == TRIG_NONE) {
2978 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2979 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2980 } else {
2981 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2982 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2983 }
2984 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2985
2986 if (cmd->start_src == TRIG_INT) {
2987 trigsel = NISTC_AO_TRIG_START1_EDGE |
2988 NISTC_AO_TRIG_START1_SYNC;
2989 } else { /* TRIG_EXT */
2990 trigsel = NISTC_AO_TRIG_START1_SEL(
2991 ni_get_reg_value_roffs(
2992 CR_CHAN(cmd->start_arg),
2993 NI_AO_StartTrigger,
2994 &devpriv->routing_tables, 1));
2995
2996 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2997 if (cmd->start_arg & CR_INVERT)
2998 trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2999 /* 0=edge detection disabled, 1=enabled */
3000 if (cmd->start_arg & CR_EDGE)
3001 trigsel |= NISTC_AO_TRIG_START1_EDGE;
3002 }
3003 ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
3004
3005 /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
3006
3007 /* sync */
3008 /* select DA_START1 as PFI6/AO_START1 when configured as an output */
3009 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
3010 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3011
3012 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3013 }
3014
ni_ao_cmd_set_counters(struct comedi_device * dev,const struct comedi_cmd * cmd)3015 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
3016 const struct comedi_cmd *cmd)
3017 {
3018 struct ni_private *devpriv = dev->private;
3019 /* Not supporting 'waveform staging' or 'local buffer with pauses' */
3020
3021 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3022 /*
3023 * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
3024 * set_trigger above. It is unclear whether we really need to re-write
3025 * this register with these values. The mhddk examples for e-series
3026 * show writing this in both places, but the examples for m-series show
3027 * a single write in the set_counters function (here).
3028 */
3029 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3030
3031 /* sync (upload number of buffer iterations -1) */
3032 /* indicate that we want to use BC_Load_A_Register as the source */
3033 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3034 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3035
3036 /*
3037 * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3038 * ignoring BC_TC, then we will need to find a way to ignore that
3039 * interrupt in continuous mode.
3040 */
3041 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3042
3043 /* sync (issue command to load number of buffer iterations -1) */
3044 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3045
3046 /* sync (upload number of updates in buffer) */
3047 /* indicate that we want to use UC_Load_A_Register as the source */
3048 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3049 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3050
3051 /*
3052 * if a user specifies '0', this automatically assumes the entire 24bit
3053 * address space is available for the (multiple iterations of single
3054 * buffer) MISB. Otherwise, stop_arg specifies the MISB length that
3055 * will be used, regardless of whether we are in continuous mode or not.
3056 * In continuous mode, the output will just iterate indefinitely over
3057 * the MISB.
3058 */
3059 {
3060 unsigned int stop_arg = cmd->stop_arg > 0 ?
3061 (cmd->stop_arg & 0xffffff) : 0xffffff;
3062
3063 if (devpriv->is_m_series) {
3064 /*
3065 * this is how the NI example code does it for m-series
3066 * boards, verified correct with 6259
3067 */
3068 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3069
3070 /* sync (issue cmd to load number of updates in MISB) */
3071 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3072 NISTC_AO_CMD1_REG);
3073 } else {
3074 ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3075
3076 /* sync (issue cmd to load number of updates in MISB) */
3077 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3078 NISTC_AO_CMD1_REG);
3079
3080 /*
3081 * sync (upload number of updates-1 in MISB)
3082 * --eseries only?
3083 */
3084 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3085 }
3086 }
3087
3088 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3089 }
3090
ni_ao_cmd_set_update(struct comedi_device * dev,const struct comedi_cmd * cmd)3091 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3092 const struct comedi_cmd *cmd)
3093 {
3094 struct ni_private *devpriv = dev->private;
3095
3096 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3097
3098 /*
3099 * zero out these bit fields to be set below. Does an ao-reset do this
3100 * automatically?
3101 */
3102 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UI_SRC_MASK |
3103 NISTC_AO_MODE1_UI_SRC_POLARITY |
3104 NISTC_AO_MODE1_UPDATE_SRC_MASK |
3105 NISTC_AO_MODE1_UPDATE_SRC_POLARITY);
3106
3107 if (cmd->scan_begin_src == TRIG_TIMER) {
3108 unsigned int trigvar;
3109
3110 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3111
3112 /*
3113 * NOTE: there are several other ways of configuring internal
3114 * updates, but we'll only support one for now: using
3115 * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3116 * START1 and first update, and also w/o local buffer mode w/
3117 * pauses.
3118 */
3119
3120 /*
3121 * This is already done above:
3122 * devpriv->ao_mode1 &= ~(
3123 * // set UPDATE_Source to UI_TC:
3124 * NISTC_AO_MODE1_UPDATE_SRC_MASK |
3125 * // set UPDATE_Source_Polarity to rising (required?)
3126 * NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3127 * // set UI_Source to AO_IN_TIMEBASE1:
3128 * NISTC_AO_MODE1_UI_SRC_MASK |
3129 * // set UI_Source_Polarity to rising (required?)
3130 * NISTC_AO_MODE1_UI_SRC_POLARITY
3131 * );
3132 */
3133
3134 /*
3135 * TODO: use ao_ui_clock_source to allow all possible signals
3136 * to be routed to UI_Source_Select. See tSTC.h for
3137 * eseries/ni67xx and tMSeries.h for mseries.
3138 */
3139
3140 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3141 CMDF_ROUND_NEAREST);
3142
3143 /*
3144 * Wait N TB3 ticks after the start trigger before
3145 * clocking (N must be >=2).
3146 */
3147 /* following line: 2-1 per STC */
3148 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3149 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3150 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3151 } else { /* TRIG_EXT */
3152 /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */
3153 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3154 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3155 ni_get_reg_value(
3156 CR_CHAN(cmd->scan_begin_arg),
3157 NI_AO_SampleClock,
3158 &devpriv->routing_tables));
3159 if (cmd->scan_begin_arg & CR_INVERT)
3160 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3161 }
3162
3163 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3164 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3165 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3166 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3167 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3168
3169 /* Configure DAQ-STC for Timed update mode */
3170 devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3171 NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3172 /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3173 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3174
3175 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3176 }
3177
ni_ao_cmd_set_channels(struct comedi_device * dev,struct comedi_subdevice * s)3178 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3179 struct comedi_subdevice *s)
3180 {
3181 struct ni_private *devpriv = dev->private;
3182 const struct comedi_cmd *cmd = &s->async->cmd;
3183 unsigned int bits = 0;
3184
3185 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3186
3187 if (devpriv->is_6xxx) {
3188 unsigned int i;
3189
3190 bits = 0;
3191 for (i = 0; i < cmd->chanlist_len; ++i) {
3192 int chan = CR_CHAN(cmd->chanlist[i]);
3193
3194 bits |= 1 << chan;
3195 ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3196 }
3197 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3198 }
3199
3200 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3201
3202 if (cmd->scan_end_arg > 1) {
3203 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3204 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3205 | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3206
3207 } else {
3208 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3209 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3210 if (devpriv->is_m_series | devpriv->is_6xxx)
3211 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3212 else
3213 bits |= NISTC_AO_OUT_CTRL_CHANS(
3214 CR_CHAN(cmd->chanlist[0]));
3215 }
3216
3217 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3218 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3219
3220 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3221 }
3222
ni_ao_cmd_set_stop_conditions(struct comedi_device * dev,const struct comedi_cmd * cmd)3223 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3224 const struct comedi_cmd *cmd)
3225 {
3226 struct ni_private *devpriv = dev->private;
3227
3228 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3229
3230 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3231 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3232
3233 /*
3234 * Since we are not supporting waveform staging, we ignore these errors:
3235 * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3236 * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3237 */
3238
3239 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3240 }
3241
ni_ao_cmd_set_fifo_mode(struct comedi_device * dev)3242 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3243 {
3244 struct ni_private *devpriv = dev->private;
3245
3246 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3247
3248 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3249 #ifdef PCIDMA
3250 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3251 #else
3252 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3253 #endif
3254 /* NOTE: this is where use_onboard_memory=True would be implemented */
3255 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3256 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3257
3258 /* enable sending of ao fifo requests (dma request) */
3259 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3260
3261 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3262
3263 /* we are not supporting boards with virtual fifos */
3264 }
3265
ni_ao_cmd_set_interrupts(struct comedi_device * dev,struct comedi_subdevice * s)3266 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3267 struct comedi_subdevice *s)
3268 {
3269 if (s->async->cmd.stop_src == TRIG_COUNT)
3270 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3271 NISTC_INTB_ENA_AO_BC_TC, 1);
3272
3273 s->async->inttrig = ni_ao_inttrig;
3274 }
3275
ni_ao_cmd(struct comedi_device * dev,struct comedi_subdevice * s)3276 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3277 {
3278 struct ni_private *devpriv = dev->private;
3279 const struct comedi_cmd *cmd = &s->async->cmd;
3280
3281 if (dev->irq == 0) {
3282 dev_err(dev->class_dev, "cannot run command without an irq");
3283 return -EIO;
3284 }
3285
3286 /* ni_ao_reset should have already been done */
3287 ni_ao_cmd_personalize(dev, cmd);
3288 /* clearing fifo and preload happens elsewhere */
3289
3290 ni_ao_cmd_set_trigger(dev, cmd);
3291 ni_ao_cmd_set_counters(dev, cmd);
3292 ni_ao_cmd_set_update(dev, cmd);
3293 ni_ao_cmd_set_channels(dev, s);
3294 ni_ao_cmd_set_stop_conditions(dev, cmd);
3295 ni_ao_cmd_set_fifo_mode(dev);
3296 ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3297 ni_ao_cmd_set_interrupts(dev, s);
3298
3299 /*
3300 * arm(ing) must happen later so that DMA can be setup and DACs
3301 * preloaded with the actual output buffer before starting.
3302 *
3303 * start(ing) must happen _after_ arming is completed. Starting can be
3304 * done either via ni_ao_inttrig, or via an external trigger.
3305 *
3306 * **Currently, ni_ao_inttrig will automatically attempt a call to
3307 * ni_ao_arm if the device still needs arming at that point. This
3308 * allows backwards compatibility.
3309 */
3310 devpriv->ao_needs_arming = 1;
3311 return 0;
3312 }
3313
3314 /* end ni_ao_cmd */
3315
ni_ao_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)3316 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3317 struct comedi_cmd *cmd)
3318 {
3319 const struct ni_board_struct *board = dev->board_ptr;
3320 struct ni_private *devpriv = dev->private;
3321 int err = 0;
3322 unsigned int tmp;
3323
3324 /* Step 1 : check if triggers are trivially valid */
3325
3326 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3327 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3328 TRIG_TIMER | TRIG_EXT);
3329 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3330 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3331 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3332
3333 if (err)
3334 return 1;
3335
3336 /* Step 2a : make sure trigger sources are unique */
3337
3338 err |= comedi_check_trigger_is_unique(cmd->start_src);
3339 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3340 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3341
3342 /* Step 2b : and mutually compatible */
3343
3344 if (err)
3345 return 2;
3346
3347 /* Step 3: check if arguments are trivially valid */
3348
3349 switch (cmd->start_src) {
3350 case TRIG_INT:
3351 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3352 break;
3353 case TRIG_EXT:
3354 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
3355 NI_AO_StartTrigger,
3356 &devpriv->routing_tables, 1);
3357 break;
3358 }
3359
3360 if (cmd->scan_begin_src == TRIG_TIMER) {
3361 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3362 board->ao_speed);
3363 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3364 devpriv->clock_ns *
3365 0xffffff);
3366 } else { /* TRIG_EXT */
3367 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3368 NI_AO_SampleClock,
3369 &devpriv->routing_tables);
3370 }
3371
3372 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3373 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3374 cmd->chanlist_len);
3375 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3376
3377 if (err)
3378 return 3;
3379
3380 /* step 4: fix up any arguments */
3381 if (cmd->scan_begin_src == TRIG_TIMER) {
3382 tmp = cmd->scan_begin_arg;
3383 cmd->scan_begin_arg =
3384 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3385 cmd->scan_begin_arg,
3386 cmd->flags));
3387 if (tmp != cmd->scan_begin_arg)
3388 err++;
3389 }
3390 if (err)
3391 return 4;
3392
3393 return 0;
3394 }
3395
ni_ao_reset(struct comedi_device * dev,struct comedi_subdevice * s)3396 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3397 {
3398 /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3399
3400 /*
3401 * In the following, the "--sync" comments are meant to denote
3402 * asynchronous boundaries for setting the registers as described in the
3403 * DAQ-STC mostly in the order also described in the DAQ-STC.
3404 */
3405
3406 struct ni_private *devpriv = dev->private;
3407
3408 ni_release_ao_mite_channel(dev);
3409
3410 /* --sync (reset AO) */
3411 if (devpriv->is_m_series)
3412 /* following example in mhddk for m-series */
3413 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3414
3415 /*--sync (start config) */
3416 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3417
3418 /*--sync (Disarm) */
3419 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3420
3421 /*
3422 * --sync
3423 * (clear bunch of registers--mseries mhddk examples do not include
3424 * this)
3425 */
3426 devpriv->ao_cmd1 = 0;
3427 devpriv->ao_cmd2 = 0;
3428 devpriv->ao_mode1 = 0;
3429 devpriv->ao_mode2 = 0;
3430 if (devpriv->is_m_series)
3431 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3432 else
3433 devpriv->ao_mode3 = 0;
3434
3435 ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3436 ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3437 ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3438 ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3439 ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3440 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3441 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3442 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3443 ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3444
3445 /*--sync (disable interrupts) */
3446 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3447
3448 /*--sync (ack) */
3449 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3450 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3451
3452 /*--not in DAQ-STC. which doc? */
3453 if (devpriv->is_6xxx) {
3454 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3455 NI671X_AO_IMMEDIATE_REG);
3456 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3457 NI611X_AO_MISC_REG);
3458 }
3459 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3460 /*--end */
3461
3462 return 0;
3463 }
3464
3465 /* digital io */
3466
ni_dio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3467 static int ni_dio_insn_config(struct comedi_device *dev,
3468 struct comedi_subdevice *s,
3469 struct comedi_insn *insn,
3470 unsigned int *data)
3471 {
3472 struct ni_private *devpriv = dev->private;
3473 int ret;
3474
3475 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3476 if (ret)
3477 return ret;
3478
3479 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3480 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3481 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3482
3483 return insn->n;
3484 }
3485
ni_dio_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3486 static int ni_dio_insn_bits(struct comedi_device *dev,
3487 struct comedi_subdevice *s,
3488 struct comedi_insn *insn,
3489 unsigned int *data)
3490 {
3491 struct ni_private *devpriv = dev->private;
3492
3493 /* Make sure we're not using the serial part of the dio */
3494 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3495 devpriv->serial_interval_ns)
3496 return -EBUSY;
3497
3498 if (comedi_dio_update_state(s, data)) {
3499 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3500 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3501 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3502 }
3503
3504 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3505
3506 return insn->n;
3507 }
3508
3509 #ifdef PCIDMA
ni_m_series_dio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3510 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3511 struct comedi_subdevice *s,
3512 struct comedi_insn *insn,
3513 unsigned int *data)
3514 {
3515 int ret;
3516
3517 if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
3518 const struct ni_board_struct *board = dev->board_ptr;
3519
3520 /* we don't care about actual channels */
3521 data[1] = board->dio_speed;
3522 data[2] = 0;
3523 return 0;
3524 }
3525
3526 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3527 if (ret)
3528 return ret;
3529
3530 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3531
3532 return insn->n;
3533 }
3534
ni_m_series_dio_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3535 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3536 struct comedi_subdevice *s,
3537 struct comedi_insn *insn,
3538 unsigned int *data)
3539 {
3540 if (comedi_dio_update_state(s, data))
3541 ni_writel(dev, s->state, NI_M_DIO_REG);
3542
3543 data[1] = ni_readl(dev, NI_M_DIO_REG);
3544
3545 return insn->n;
3546 }
3547
ni_cdio_check_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)3548 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3549 struct comedi_subdevice *s,
3550 struct comedi_cmd *cmd)
3551 {
3552 int i;
3553
3554 for (i = 0; i < cmd->chanlist_len; ++i) {
3555 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3556
3557 if (chan != i)
3558 return -EINVAL;
3559 }
3560
3561 return 0;
3562 }
3563
ni_cdio_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)3564 static int ni_cdio_cmdtest(struct comedi_device *dev,
3565 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3566 {
3567 struct ni_private *devpriv = dev->private;
3568 unsigned int bytes_per_scan;
3569 int err = 0;
3570
3571 /* Step 1 : check if triggers are trivially valid */
3572
3573 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3574 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3575 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3576 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3577 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3578
3579 if (err)
3580 return 1;
3581
3582 /* Step 2a : make sure trigger sources are unique */
3583 /* Step 2b : and mutually compatible */
3584
3585 /* Step 3: check if arguments are trivially valid */
3586
3587 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3588
3589 /*
3590 * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3591 * for completeness, test whether the cmd is output or input?
3592 */
3593 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3594 NI_DO_SampleClock,
3595 &devpriv->routing_tables);
3596 if (CR_RANGE(cmd->scan_begin_arg) != 0 ||
3597 CR_AREF(cmd->scan_begin_arg) != 0)
3598 err |= -EINVAL;
3599
3600 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3601 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3602 cmd->chanlist_len);
3603 bytes_per_scan = comedi_bytes_per_scan_cmd(s, cmd);
3604 if (bytes_per_scan) {
3605 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3606 s->async->prealloc_bufsz /
3607 bytes_per_scan);
3608 }
3609
3610 if (err)
3611 return 3;
3612
3613 /* Step 4: fix up any arguments */
3614
3615 /* Step 5: check channel list if it exists */
3616
3617 if (cmd->chanlist && cmd->chanlist_len > 0)
3618 err |= ni_cdio_check_chanlist(dev, s, cmd);
3619
3620 if (err)
3621 return 5;
3622
3623 return 0;
3624 }
3625
ni_cdo_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)3626 static int ni_cdo_inttrig(struct comedi_device *dev,
3627 struct comedi_subdevice *s,
3628 unsigned int trig_num)
3629 {
3630 struct comedi_cmd *cmd = &s->async->cmd;
3631 const unsigned int timeout = 1000;
3632 int retval = 0;
3633 unsigned int i;
3634 struct ni_private *devpriv = dev->private;
3635 unsigned long flags;
3636
3637 if (trig_num != cmd->start_arg)
3638 return -EINVAL;
3639
3640 s->async->inttrig = NULL;
3641
3642 /* read alloc the entire buffer */
3643 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3644
3645 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3646 if (devpriv->cdo_mite_chan) {
3647 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3648 mite_dma_arm(devpriv->cdo_mite_chan);
3649 } else {
3650 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3651 retval = -EIO;
3652 }
3653 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3654 if (retval < 0)
3655 return retval;
3656
3657 /*
3658 * XXX not sure what interrupt C group does
3659 * wait for dma to fill output fifo
3660 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3661 */
3662 for (i = 0; i < timeout; ++i) {
3663 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3664 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3665 break;
3666 usleep_range(10, 100);
3667 }
3668 if (i == timeout) {
3669 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3670 s->cancel(dev, s);
3671 return -EIO;
3672 }
3673 ni_writel(dev, NI_M_CDO_CMD_ARM |
3674 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3675 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3676 NI_M_CDIO_CMD_REG);
3677 return retval;
3678 }
3679
ni_cdio_cmd(struct comedi_device * dev,struct comedi_subdevice * s)3680 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3681 {
3682 struct ni_private *devpriv = dev->private;
3683 const struct comedi_cmd *cmd = &s->async->cmd;
3684 unsigned int cdo_mode_bits;
3685 int retval;
3686
3687 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3688 /*
3689 * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3690 * for completeness, test whether the cmd is output or input(?)
3691 */
3692 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3693 NI_M_CDO_MODE_HALT_ON_ERROR |
3694 NI_M_CDO_MODE_SAMPLE_SRC(
3695 ni_get_reg_value(
3696 CR_CHAN(cmd->scan_begin_arg),
3697 NI_DO_SampleClock,
3698 &devpriv->routing_tables));
3699 if (cmd->scan_begin_arg & CR_INVERT)
3700 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3701 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3702 if (s->io_bits) {
3703 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3704 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3705 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3706 } else {
3707 dev_err(dev->class_dev,
3708 "attempted to run digital output command with no lines configured as outputs\n");
3709 return -EIO;
3710 }
3711 retval = ni_request_cdo_mite_channel(dev);
3712 if (retval < 0)
3713 return retval;
3714
3715 ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3716 s->async->prealloc_bufsz /
3717 comedi_bytes_per_scan(s));
3718
3719 s->async->inttrig = ni_cdo_inttrig;
3720
3721 return 0;
3722 }
3723
ni_cdio_cancel(struct comedi_device * dev,struct comedi_subdevice * s)3724 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3725 {
3726 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3727 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3728 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3729 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3730 NI_M_CDIO_CMD_REG);
3731 /*
3732 * XXX not sure what interrupt C group does
3733 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3734 */
3735 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3736 ni_release_cdo_mite_channel(dev);
3737 return 0;
3738 }
3739
handle_cdio_interrupt(struct comedi_device * dev)3740 static void handle_cdio_interrupt(struct comedi_device *dev)
3741 {
3742 struct ni_private *devpriv = dev->private;
3743 unsigned int cdio_status;
3744 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3745 unsigned long flags;
3746
3747 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3748 if (devpriv->cdo_mite_chan)
3749 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3750 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3751
3752 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3753 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3754 /* XXX just guessing this is needed and does something useful */
3755 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3756 NI_M_CDIO_CMD_REG);
3757 s->async->events |= COMEDI_CB_OVERFLOW;
3758 }
3759 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3760 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3761 NI_M_CDIO_CMD_REG);
3762 /* s->async->events |= COMEDI_CB_EOA; */
3763 }
3764 comedi_handle_events(dev, s);
3765 }
3766 #endif /* PCIDMA */
3767
ni_serial_hw_readwrite8(struct comedi_device * dev,struct comedi_subdevice * s,unsigned char data_out,unsigned char * data_in)3768 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3769 struct comedi_subdevice *s,
3770 unsigned char data_out,
3771 unsigned char *data_in)
3772 {
3773 struct ni_private *devpriv = dev->private;
3774 unsigned int status1;
3775 int err = 0, count = 20;
3776
3777 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3778 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3779 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3780
3781 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3782 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3783 err = -EBUSY;
3784 goto error;
3785 }
3786
3787 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3788 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3789 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3790
3791 /* Wait until STC says we're done, but don't loop infinitely. */
3792 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3793 NISTC_STATUS1_SERIO_IN_PROG) {
3794 /* Delay one bit per loop */
3795 udelay((devpriv->serial_interval_ns + 999) / 1000);
3796 if (--count < 0) {
3797 dev_err(dev->class_dev,
3798 "SPI serial I/O didn't finish in time!\n");
3799 err = -ETIME;
3800 goto error;
3801 }
3802 }
3803
3804 /*
3805 * Delay for last bit. This delay is absolutely necessary, because
3806 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3807 */
3808 udelay((devpriv->serial_interval_ns + 999) / 1000);
3809
3810 if (data_in)
3811 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3812
3813 error:
3814 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3815
3816 return err;
3817 }
3818
ni_serial_sw_readwrite8(struct comedi_device * dev,struct comedi_subdevice * s,unsigned char data_out,unsigned char * data_in)3819 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3820 struct comedi_subdevice *s,
3821 unsigned char data_out,
3822 unsigned char *data_in)
3823 {
3824 struct ni_private *devpriv = dev->private;
3825 unsigned char mask, input = 0;
3826
3827 /* Wait for one bit before transfer */
3828 udelay((devpriv->serial_interval_ns + 999) / 1000);
3829
3830 for (mask = 0x80; mask; mask >>= 1) {
3831 /*
3832 * Output current bit; note that we cannot touch s->state
3833 * because it is a per-subdevice field, and serial is
3834 * a separate subdevice from DIO.
3835 */
3836 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3837 if (data_out & mask)
3838 devpriv->dio_output |= NISTC_DIO_SDOUT;
3839 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3840
3841 /*
3842 * Assert SDCLK (active low, inverted), wait for half of
3843 * the delay, deassert SDCLK, and wait for the other half.
3844 */
3845 devpriv->dio_control |= NISTC_DIO_SDCLK;
3846 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3847
3848 udelay((devpriv->serial_interval_ns + 999) / 2000);
3849
3850 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3851 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3852
3853 udelay((devpriv->serial_interval_ns + 999) / 2000);
3854
3855 /* Input current bit */
3856 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3857 input |= mask;
3858 }
3859
3860 if (data_in)
3861 *data_in = input;
3862
3863 return 0;
3864 }
3865
ni_serial_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3866 static int ni_serial_insn_config(struct comedi_device *dev,
3867 struct comedi_subdevice *s,
3868 struct comedi_insn *insn,
3869 unsigned int *data)
3870 {
3871 struct ni_private *devpriv = dev->private;
3872 unsigned int clk_fout = devpriv->clock_and_fout;
3873 int err = insn->n;
3874 unsigned char byte_out, byte_in = 0;
3875
3876 if (insn->n != 2)
3877 return -EINVAL;
3878
3879 switch (data[0]) {
3880 case INSN_CONFIG_SERIAL_CLOCK:
3881 devpriv->serial_hw_mode = 1;
3882 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3883
3884 if (data[1] == SERIAL_DISABLED) {
3885 devpriv->serial_hw_mode = 0;
3886 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3887 NISTC_DIO_SDCLK);
3888 data[1] = SERIAL_DISABLED;
3889 devpriv->serial_interval_ns = data[1];
3890 } else if (data[1] <= SERIAL_600NS) {
3891 /*
3892 * Warning: this clock speed is too fast to reliably
3893 * control SCXI.
3894 */
3895 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3896 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3897 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3898 data[1] = SERIAL_600NS;
3899 devpriv->serial_interval_ns = data[1];
3900 } else if (data[1] <= SERIAL_1_2US) {
3901 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3902 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3903 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3904 data[1] = SERIAL_1_2US;
3905 devpriv->serial_interval_ns = data[1];
3906 } else if (data[1] <= SERIAL_10US) {
3907 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3908 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3909 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3910 /*
3911 * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3912 * 600ns/1.2us. If you turn divide_by_2 off with the
3913 * slow clock, you will still get 10us, except then
3914 * all your delays are wrong.
3915 */
3916 data[1] = SERIAL_10US;
3917 devpriv->serial_interval_ns = data[1];
3918 } else {
3919 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3920 NISTC_DIO_SDCLK);
3921 devpriv->serial_hw_mode = 0;
3922 data[1] = (data[1] / 1000) * 1000;
3923 devpriv->serial_interval_ns = data[1];
3924 }
3925 devpriv->clock_and_fout = clk_fout;
3926
3927 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3928 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3929 return 1;
3930
3931 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3932
3933 if (devpriv->serial_interval_ns == 0)
3934 return -EINVAL;
3935
3936 byte_out = data[1] & 0xFF;
3937
3938 if (devpriv->serial_hw_mode) {
3939 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3940 &byte_in);
3941 } else if (devpriv->serial_interval_ns > 0) {
3942 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3943 &byte_in);
3944 } else {
3945 dev_err(dev->class_dev, "serial disabled!\n");
3946 return -EINVAL;
3947 }
3948 if (err < 0)
3949 return err;
3950 data[1] = byte_in & 0xFF;
3951 return insn->n;
3952
3953 break;
3954 default:
3955 return -EINVAL;
3956 }
3957 }
3958
init_ao_67xx(struct comedi_device * dev,struct comedi_subdevice * s)3959 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3960 {
3961 int i;
3962
3963 for (i = 0; i < s->n_chan; i++) {
3964 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3965 NI67XX_AO_CFG2_REG);
3966 }
3967 ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3968 }
3969
3970 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3971 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3972 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3973 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3974 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3975 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3976 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
3977 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3978 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
3979 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3980 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3981 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3982 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3983 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3984 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3985 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3986 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3987 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3988 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3989 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3990 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3991 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3992 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3993 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
3994 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
3995 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3996 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3997 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3998 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3999 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
4000 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
4001 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
4002 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
4003 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
4004 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
4005 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
4006 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
4007 };
4008
ni_gpct_to_stc_register(struct comedi_device * dev,enum ni_gpct_register reg)4009 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
4010 enum ni_gpct_register reg)
4011 {
4012 const struct mio_regmap *regmap;
4013
4014 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
4015 regmap = &ni_gpct_to_stc_regmap[reg];
4016 } else {
4017 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
4018 __func__, reg);
4019 return 0;
4020 }
4021
4022 return regmap->mio_reg;
4023 }
4024
ni_gpct_write_register(struct ni_gpct * counter,unsigned int bits,enum ni_gpct_register reg)4025 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
4026 enum ni_gpct_register reg)
4027 {
4028 struct comedi_device *dev = counter->counter_dev->dev;
4029 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4030
4031 if (stc_register == 0)
4032 return;
4033
4034 switch (reg) {
4035 /* m-series only registers */
4036 case NITIO_G0_CNT_MODE:
4037 case NITIO_G1_CNT_MODE:
4038 case NITIO_G0_GATE2:
4039 case NITIO_G1_GATE2:
4040 case NITIO_G0_DMA_CFG:
4041 case NITIO_G1_DMA_CFG:
4042 case NITIO_G0_ABZ:
4043 case NITIO_G1_ABZ:
4044 ni_writew(dev, bits, stc_register);
4045 break;
4046
4047 /* 32 bit registers */
4048 case NITIO_G0_LOADA:
4049 case NITIO_G1_LOADA:
4050 case NITIO_G0_LOADB:
4051 case NITIO_G1_LOADB:
4052 ni_stc_writel(dev, bits, stc_register);
4053 break;
4054
4055 /* 16 bit registers */
4056 case NITIO_G0_INT_ENA:
4057 ni_set_bitfield(dev, stc_register,
4058 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
4059 bits);
4060 break;
4061 case NITIO_G1_INT_ENA:
4062 ni_set_bitfield(dev, stc_register,
4063 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
4064 bits);
4065 break;
4066 default:
4067 ni_stc_writew(dev, bits, stc_register);
4068 }
4069 }
4070
ni_gpct_read_register(struct ni_gpct * counter,enum ni_gpct_register reg)4071 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4072 enum ni_gpct_register reg)
4073 {
4074 struct comedi_device *dev = counter->counter_dev->dev;
4075 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4076
4077 if (stc_register == 0)
4078 return 0;
4079
4080 switch (reg) {
4081 /* m-series only registers */
4082 case NITIO_G0_DMA_STATUS:
4083 case NITIO_G1_DMA_STATUS:
4084 return ni_readw(dev, stc_register);
4085
4086 /* 32 bit registers */
4087 case NITIO_G0_HW_SAVE:
4088 case NITIO_G1_HW_SAVE:
4089 case NITIO_G0_SW_SAVE:
4090 case NITIO_G1_SW_SAVE:
4091 return ni_stc_readl(dev, stc_register);
4092
4093 /* 16 bit registers */
4094 default:
4095 return ni_stc_readw(dev, stc_register);
4096 }
4097 }
4098
ni_freq_out_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4099 static int ni_freq_out_insn_read(struct comedi_device *dev,
4100 struct comedi_subdevice *s,
4101 struct comedi_insn *insn,
4102 unsigned int *data)
4103 {
4104 struct ni_private *devpriv = dev->private;
4105 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4106 int i;
4107
4108 for (i = 0; i < insn->n; i++)
4109 data[i] = val;
4110
4111 return insn->n;
4112 }
4113
ni_freq_out_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4114 static int ni_freq_out_insn_write(struct comedi_device *dev,
4115 struct comedi_subdevice *s,
4116 struct comedi_insn *insn,
4117 unsigned int *data)
4118 {
4119 struct ni_private *devpriv = dev->private;
4120
4121 if (insn->n) {
4122 unsigned int val = data[insn->n - 1];
4123
4124 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4125 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4126 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4127
4128 /* use the last data value to set the fout divider */
4129 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4130
4131 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4132 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4133 }
4134 return insn->n;
4135 }
4136
ni_freq_out_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4137 static int ni_freq_out_insn_config(struct comedi_device *dev,
4138 struct comedi_subdevice *s,
4139 struct comedi_insn *insn,
4140 unsigned int *data)
4141 {
4142 struct ni_private *devpriv = dev->private;
4143
4144 switch (data[0]) {
4145 case INSN_CONFIG_SET_CLOCK_SRC:
4146 switch (data[1]) {
4147 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4148 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4149 break;
4150 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4151 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4152 break;
4153 default:
4154 return -EINVAL;
4155 }
4156 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4157 break;
4158 case INSN_CONFIG_GET_CLOCK_SRC:
4159 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4160 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4161 data[2] = TIMEBASE_2_NS;
4162 } else {
4163 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4164 data[2] = TIMEBASE_1_NS * 2;
4165 }
4166 break;
4167 default:
4168 return -EINVAL;
4169 }
4170 return insn->n;
4171 }
4172
ni_8255_callback(struct comedi_device * dev,int dir,int port,int data,unsigned long iobase)4173 static int ni_8255_callback(struct comedi_device *dev,
4174 int dir, int port, int data, unsigned long iobase)
4175 {
4176 if (dir) {
4177 ni_writeb(dev, data, iobase + 2 * port);
4178 return 0;
4179 }
4180
4181 return ni_readb(dev, iobase + 2 * port);
4182 }
4183
ni_get_pwm_config(struct comedi_device * dev,unsigned int * data)4184 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4185 {
4186 struct ni_private *devpriv = dev->private;
4187
4188 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4189 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4190 return 3;
4191 }
4192
ni_m_series_pwm_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4193 static int ni_m_series_pwm_config(struct comedi_device *dev,
4194 struct comedi_subdevice *s,
4195 struct comedi_insn *insn,
4196 unsigned int *data)
4197 {
4198 struct ni_private *devpriv = dev->private;
4199 unsigned int up_count, down_count;
4200
4201 switch (data[0]) {
4202 case INSN_CONFIG_PWM_OUTPUT:
4203 switch (data[1]) {
4204 case CMDF_ROUND_NEAREST:
4205 up_count = DIV_ROUND_CLOSEST(data[2],
4206 devpriv->clock_ns);
4207 break;
4208 case CMDF_ROUND_DOWN:
4209 up_count = data[2] / devpriv->clock_ns;
4210 break;
4211 case CMDF_ROUND_UP:
4212 up_count =
4213 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4214 break;
4215 default:
4216 return -EINVAL;
4217 }
4218 switch (data[3]) {
4219 case CMDF_ROUND_NEAREST:
4220 down_count = DIV_ROUND_CLOSEST(data[4],
4221 devpriv->clock_ns);
4222 break;
4223 case CMDF_ROUND_DOWN:
4224 down_count = data[4] / devpriv->clock_ns;
4225 break;
4226 case CMDF_ROUND_UP:
4227 down_count =
4228 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4229 break;
4230 default:
4231 return -EINVAL;
4232 }
4233 if (up_count * devpriv->clock_ns != data[2] ||
4234 down_count * devpriv->clock_ns != data[4]) {
4235 data[2] = up_count * devpriv->clock_ns;
4236 data[4] = down_count * devpriv->clock_ns;
4237 return -EAGAIN;
4238 }
4239 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4240 NI_M_CAL_PWM_LOW_TIME(down_count),
4241 NI_M_CAL_PWM_REG);
4242 devpriv->pwm_up_count = up_count;
4243 devpriv->pwm_down_count = down_count;
4244 return 5;
4245 case INSN_CONFIG_GET_PWM_OUTPUT:
4246 return ni_get_pwm_config(dev, data);
4247 default:
4248 return -EINVAL;
4249 }
4250 return 0;
4251 }
4252
ni_6143_pwm_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4253 static int ni_6143_pwm_config(struct comedi_device *dev,
4254 struct comedi_subdevice *s,
4255 struct comedi_insn *insn,
4256 unsigned int *data)
4257 {
4258 struct ni_private *devpriv = dev->private;
4259 unsigned int up_count, down_count;
4260
4261 switch (data[0]) {
4262 case INSN_CONFIG_PWM_OUTPUT:
4263 switch (data[1]) {
4264 case CMDF_ROUND_NEAREST:
4265 up_count = DIV_ROUND_CLOSEST(data[2],
4266 devpriv->clock_ns);
4267 break;
4268 case CMDF_ROUND_DOWN:
4269 up_count = data[2] / devpriv->clock_ns;
4270 break;
4271 case CMDF_ROUND_UP:
4272 up_count =
4273 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4274 break;
4275 default:
4276 return -EINVAL;
4277 }
4278 switch (data[3]) {
4279 case CMDF_ROUND_NEAREST:
4280 down_count = DIV_ROUND_CLOSEST(data[4],
4281 devpriv->clock_ns);
4282 break;
4283 case CMDF_ROUND_DOWN:
4284 down_count = data[4] / devpriv->clock_ns;
4285 break;
4286 case CMDF_ROUND_UP:
4287 down_count =
4288 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4289 break;
4290 default:
4291 return -EINVAL;
4292 }
4293 if (up_count * devpriv->clock_ns != data[2] ||
4294 down_count * devpriv->clock_ns != data[4]) {
4295 data[2] = up_count * devpriv->clock_ns;
4296 data[4] = down_count * devpriv->clock_ns;
4297 return -EAGAIN;
4298 }
4299 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4300 devpriv->pwm_up_count = up_count;
4301 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4302 devpriv->pwm_down_count = down_count;
4303 return 5;
4304 case INSN_CONFIG_GET_PWM_OUTPUT:
4305 return ni_get_pwm_config(dev, data);
4306 default:
4307 return -EINVAL;
4308 }
4309 return 0;
4310 }
4311
pack_mb88341(int addr,int val,int * bitstring)4312 static int pack_mb88341(int addr, int val, int *bitstring)
4313 {
4314 /*
4315 * Fujitsu MB 88341
4316 * Note that address bits are reversed. Thanks to
4317 * Ingo Keen for noticing this.
4318 *
4319 * Note also that the 88341 expects address values from
4320 * 1-12, whereas we use channel numbers 0-11. The NI
4321 * docs use 1-12, also, so be careful here.
4322 */
4323 addr++;
4324 *bitstring = ((addr & 0x1) << 11) |
4325 ((addr & 0x2) << 9) |
4326 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4327 return 12;
4328 }
4329
pack_dac8800(int addr,int val,int * bitstring)4330 static int pack_dac8800(int addr, int val, int *bitstring)
4331 {
4332 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4333 return 11;
4334 }
4335
pack_dac8043(int addr,int val,int * bitstring)4336 static int pack_dac8043(int addr, int val, int *bitstring)
4337 {
4338 *bitstring = val & 0xfff;
4339 return 12;
4340 }
4341
pack_ad8522(int addr,int val,int * bitstring)4342 static int pack_ad8522(int addr, int val, int *bitstring)
4343 {
4344 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4345 return 16;
4346 }
4347
pack_ad8804(int addr,int val,int * bitstring)4348 static int pack_ad8804(int addr, int val, int *bitstring)
4349 {
4350 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4351 return 12;
4352 }
4353
pack_ad8842(int addr,int val,int * bitstring)4354 static int pack_ad8842(int addr, int val, int *bitstring)
4355 {
4356 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4357 return 12;
4358 }
4359
4360 struct caldac_struct {
4361 int n_chans;
4362 int n_bits;
4363 int (*packbits)(int address, int value, int *bitstring);
4364 };
4365
4366 static struct caldac_struct caldacs[] = {
4367 [mb88341] = {12, 8, pack_mb88341},
4368 [dac8800] = {8, 8, pack_dac8800},
4369 [dac8043] = {1, 12, pack_dac8043},
4370 [ad8522] = {2, 12, pack_ad8522},
4371 [ad8804] = {12, 8, pack_ad8804},
4372 [ad8842] = {8, 8, pack_ad8842},
4373 [ad8804_debug] = {16, 8, pack_ad8804},
4374 };
4375
ni_write_caldac(struct comedi_device * dev,int addr,int val)4376 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4377 {
4378 const struct ni_board_struct *board = dev->board_ptr;
4379 struct ni_private *devpriv = dev->private;
4380 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4381 unsigned int cmd;
4382 int i;
4383 int type;
4384
4385 if (devpriv->caldacs[addr] == val)
4386 return;
4387 devpriv->caldacs[addr] = val;
4388
4389 for (i = 0; i < 3; i++) {
4390 type = board->caldac[i];
4391 if (type == caldac_none)
4392 break;
4393 if (addr < caldacs[type].n_chans) {
4394 bits = caldacs[type].packbits(addr, val, &bitstring);
4395 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4396 break;
4397 }
4398 addr -= caldacs[type].n_chans;
4399 }
4400
4401 /* bits will be 0 if there is no caldac for the given addr */
4402 if (bits == 0)
4403 return;
4404
4405 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4406 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4407 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4408 udelay(1);
4409 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4410 udelay(1);
4411 }
4412 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4413 udelay(1);
4414 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4415 }
4416
ni_calib_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4417 static int ni_calib_insn_write(struct comedi_device *dev,
4418 struct comedi_subdevice *s,
4419 struct comedi_insn *insn,
4420 unsigned int *data)
4421 {
4422 if (insn->n) {
4423 /* only bother writing the last sample to the channel */
4424 ni_write_caldac(dev, CR_CHAN(insn->chanspec),
4425 data[insn->n - 1]);
4426 }
4427
4428 return insn->n;
4429 }
4430
ni_calib_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4431 static int ni_calib_insn_read(struct comedi_device *dev,
4432 struct comedi_subdevice *s,
4433 struct comedi_insn *insn,
4434 unsigned int *data)
4435 {
4436 struct ni_private *devpriv = dev->private;
4437 unsigned int i;
4438
4439 for (i = 0; i < insn->n; i++)
4440 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4441
4442 return insn->n;
4443 }
4444
caldac_setup(struct comedi_device * dev,struct comedi_subdevice * s)4445 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4446 {
4447 const struct ni_board_struct *board = dev->board_ptr;
4448 struct ni_private *devpriv = dev->private;
4449 int i, j;
4450 int n_dacs;
4451 int n_chans = 0;
4452 int n_bits;
4453 int diffbits = 0;
4454 int type;
4455 int chan;
4456
4457 type = board->caldac[0];
4458 if (type == caldac_none)
4459 return;
4460 n_bits = caldacs[type].n_bits;
4461 for (i = 0; i < 3; i++) {
4462 type = board->caldac[i];
4463 if (type == caldac_none)
4464 break;
4465 if (caldacs[type].n_bits != n_bits)
4466 diffbits = 1;
4467 n_chans += caldacs[type].n_chans;
4468 }
4469 n_dacs = i;
4470 s->n_chan = n_chans;
4471
4472 if (diffbits) {
4473 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4474
4475 if (n_chans > MAX_N_CALDACS)
4476 dev_err(dev->class_dev,
4477 "BUG! MAX_N_CALDACS too small\n");
4478 s->maxdata_list = maxdata_list;
4479 chan = 0;
4480 for (i = 0; i < n_dacs; i++) {
4481 type = board->caldac[i];
4482 for (j = 0; j < caldacs[type].n_chans; j++) {
4483 maxdata_list[chan] =
4484 (1 << caldacs[type].n_bits) - 1;
4485 chan++;
4486 }
4487 }
4488
4489 for (chan = 0; chan < s->n_chan; chan++)
4490 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4491 } else {
4492 type = board->caldac[0];
4493 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4494
4495 for (chan = 0; chan < s->n_chan; chan++)
4496 ni_write_caldac(dev, i, s->maxdata / 2);
4497 }
4498 }
4499
ni_read_eeprom(struct comedi_device * dev,int addr)4500 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4501 {
4502 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4503 int bit;
4504 int bitstring;
4505
4506 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4507 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4508 for (bit = 0x8000; bit; bit >>= 1) {
4509 if (bit & bitstring)
4510 cmd |= NI_E_SERIAL_CMD_SDATA;
4511 else
4512 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4513
4514 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4515 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4516 }
4517 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4518 bitstring = 0;
4519 for (bit = 0x80; bit; bit >>= 1) {
4520 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4521 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4522 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4523 bitstring |= bit;
4524 }
4525 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4526
4527 return bitstring;
4528 }
4529
ni_eeprom_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4530 static int ni_eeprom_insn_read(struct comedi_device *dev,
4531 struct comedi_subdevice *s,
4532 struct comedi_insn *insn,
4533 unsigned int *data)
4534 {
4535 unsigned int val;
4536 unsigned int i;
4537
4538 if (insn->n) {
4539 val = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4540 for (i = 0; i < insn->n; i++)
4541 data[i] = val;
4542 }
4543 return insn->n;
4544 }
4545
ni_m_series_eeprom_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4546 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4547 struct comedi_subdevice *s,
4548 struct comedi_insn *insn,
4549 unsigned int *data)
4550 {
4551 struct ni_private *devpriv = dev->private;
4552 unsigned int i;
4553
4554 for (i = 0; i < insn->n; i++)
4555 data[i] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4556
4557 return insn->n;
4558 }
4559
ni_old_get_pfi_routing(struct comedi_device * dev,unsigned int chan)4560 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4561 unsigned int chan)
4562 {
4563 /* pre-m-series boards have fixed signals on pfi pins */
4564 switch (chan) {
4565 case 0:
4566 return NI_PFI_OUTPUT_AI_START1;
4567 case 1:
4568 return NI_PFI_OUTPUT_AI_START2;
4569 case 2:
4570 return NI_PFI_OUTPUT_AI_CONVERT;
4571 case 3:
4572 return NI_PFI_OUTPUT_G_SRC1;
4573 case 4:
4574 return NI_PFI_OUTPUT_G_GATE1;
4575 case 5:
4576 return NI_PFI_OUTPUT_AO_UPDATE_N;
4577 case 6:
4578 return NI_PFI_OUTPUT_AO_START1;
4579 case 7:
4580 return NI_PFI_OUTPUT_AI_START_PULSE;
4581 case 8:
4582 return NI_PFI_OUTPUT_G_SRC0;
4583 case 9:
4584 return NI_PFI_OUTPUT_G_GATE0;
4585 default:
4586 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4587 break;
4588 }
4589 return 0;
4590 }
4591
ni_old_set_pfi_routing(struct comedi_device * dev,unsigned int chan,unsigned int source)4592 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4593 unsigned int chan, unsigned int source)
4594 {
4595 /* pre-m-series boards have fixed signals on pfi pins */
4596 if (source != ni_old_get_pfi_routing(dev, chan))
4597 return -EINVAL;
4598 return 2;
4599 }
4600
ni_m_series_get_pfi_routing(struct comedi_device * dev,unsigned int chan)4601 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4602 unsigned int chan)
4603 {
4604 struct ni_private *devpriv = dev->private;
4605 const unsigned int array_offset = chan / 3;
4606
4607 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4608 devpriv->pfi_output_select_reg[array_offset]);
4609 }
4610
ni_m_series_set_pfi_routing(struct comedi_device * dev,unsigned int chan,unsigned int source)4611 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4612 unsigned int chan, unsigned int source)
4613 {
4614 struct ni_private *devpriv = dev->private;
4615 unsigned int index = chan / 3;
4616 unsigned short val = devpriv->pfi_output_select_reg[index];
4617
4618 if ((source & 0x1f) != source)
4619 return -EINVAL;
4620
4621 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4622 val |= NI_M_PFI_OUT_SEL(chan, source);
4623 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4624 devpriv->pfi_output_select_reg[index] = val;
4625
4626 return 2;
4627 }
4628
ni_get_pfi_routing(struct comedi_device * dev,unsigned int chan)4629 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4630 unsigned int chan)
4631 {
4632 struct ni_private *devpriv = dev->private;
4633
4634 if (chan >= NI_PFI(0)) {
4635 /* allow new and old names of pfi channels to work. */
4636 chan -= NI_PFI(0);
4637 }
4638 return (devpriv->is_m_series)
4639 ? ni_m_series_get_pfi_routing(dev, chan)
4640 : ni_old_get_pfi_routing(dev, chan);
4641 }
4642
4643 /* Sets the output mux for the specified PFI channel. */
ni_set_pfi_routing(struct comedi_device * dev,unsigned int chan,unsigned int source)4644 static int ni_set_pfi_routing(struct comedi_device *dev,
4645 unsigned int chan, unsigned int source)
4646 {
4647 struct ni_private *devpriv = dev->private;
4648
4649 if (chan >= NI_PFI(0)) {
4650 /* allow new and old names of pfi channels to work. */
4651 chan -= NI_PFI(0);
4652 }
4653 return (devpriv->is_m_series)
4654 ? ni_m_series_set_pfi_routing(dev, chan, source)
4655 : ni_old_set_pfi_routing(dev, chan, source);
4656 }
4657
ni_config_pfi_filter(struct comedi_device * dev,unsigned int chan,enum ni_pfi_filter_select filter)4658 static int ni_config_pfi_filter(struct comedi_device *dev,
4659 unsigned int chan,
4660 enum ni_pfi_filter_select filter)
4661 {
4662 struct ni_private *devpriv = dev->private;
4663 unsigned int bits;
4664
4665 if (!devpriv->is_m_series)
4666 return -ENOTSUPP;
4667
4668 if (chan >= NI_PFI(0)) {
4669 /* allow new and old names of pfi channels to work. */
4670 chan -= NI_PFI(0);
4671 }
4672
4673 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4674 bits &= ~NI_M_PFI_FILTER_SEL_MASK(chan);
4675 bits |= NI_M_PFI_FILTER_SEL(chan, filter);
4676 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4677 return 0;
4678 }
4679
ni_set_pfi_direction(struct comedi_device * dev,int chan,unsigned int direction)4680 static void ni_set_pfi_direction(struct comedi_device *dev, int chan,
4681 unsigned int direction)
4682 {
4683 if (chan >= NI_PFI(0)) {
4684 /* allow new and old names of pfi channels to work. */
4685 chan -= NI_PFI(0);
4686 }
4687 direction = (direction == COMEDI_OUTPUT) ? 1u : 0u;
4688 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, direction);
4689 }
4690
ni_get_pfi_direction(struct comedi_device * dev,int chan)4691 static int ni_get_pfi_direction(struct comedi_device *dev, int chan)
4692 {
4693 struct ni_private *devpriv = dev->private;
4694
4695 if (chan >= NI_PFI(0)) {
4696 /* allow new and old names of pfi channels to work. */
4697 chan -= NI_PFI(0);
4698 }
4699 return devpriv->io_bidirection_pin_reg & (1 << chan) ?
4700 COMEDI_OUTPUT : COMEDI_INPUT;
4701 }
4702
ni_pfi_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4703 static int ni_pfi_insn_config(struct comedi_device *dev,
4704 struct comedi_subdevice *s,
4705 struct comedi_insn *insn,
4706 unsigned int *data)
4707 {
4708 unsigned int chan;
4709
4710 if (insn->n < 1)
4711 return -EINVAL;
4712
4713 chan = CR_CHAN(insn->chanspec);
4714
4715 switch (data[0]) {
4716 case COMEDI_OUTPUT:
4717 case COMEDI_INPUT:
4718 ni_set_pfi_direction(dev, chan, data[0]);
4719 break;
4720 case INSN_CONFIG_DIO_QUERY:
4721 data[1] = ni_get_pfi_direction(dev, chan);
4722 break;
4723 case INSN_CONFIG_SET_ROUTING:
4724 return ni_set_pfi_routing(dev, chan, data[1]);
4725 case INSN_CONFIG_GET_ROUTING:
4726 data[1] = ni_get_pfi_routing(dev, chan);
4727 break;
4728 case INSN_CONFIG_FILTER:
4729 return ni_config_pfi_filter(dev, chan, data[1]);
4730 default:
4731 return -EINVAL;
4732 }
4733 return 0;
4734 }
4735
ni_pfi_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4736 static int ni_pfi_insn_bits(struct comedi_device *dev,
4737 struct comedi_subdevice *s,
4738 struct comedi_insn *insn,
4739 unsigned int *data)
4740 {
4741 struct ni_private *devpriv = dev->private;
4742
4743 if (!devpriv->is_m_series)
4744 return -ENOTSUPP;
4745
4746 if (comedi_dio_update_state(s, data))
4747 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4748
4749 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4750
4751 return insn->n;
4752 }
4753
cs5529_wait_for_idle(struct comedi_device * dev)4754 static int cs5529_wait_for_idle(struct comedi_device *dev)
4755 {
4756 unsigned short status;
4757 const int timeout = HZ;
4758 int i;
4759
4760 for (i = 0; i < timeout; i++) {
4761 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4762 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4763 break;
4764 set_current_state(TASK_INTERRUPTIBLE);
4765 if (schedule_timeout(1))
4766 return -EIO;
4767 }
4768 if (i == timeout) {
4769 dev_err(dev->class_dev, "timeout\n");
4770 return -ETIME;
4771 }
4772 return 0;
4773 }
4774
cs5529_command(struct comedi_device * dev,unsigned short value)4775 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4776 {
4777 static const int timeout = 100;
4778 int i;
4779
4780 ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4781 /* give time for command to start being serially clocked into cs5529.
4782 * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4783 * set before we exit this function.
4784 */
4785 for (i = 0; i < timeout; i++) {
4786 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4787 NI67XX_CAL_STATUS_BUSY)
4788 break;
4789 udelay(1);
4790 }
4791 if (i == timeout)
4792 dev_err(dev->class_dev,
4793 "possible problem - never saw adc go busy?\n");
4794 }
4795
cs5529_do_conversion(struct comedi_device * dev,unsigned short * data)4796 static int cs5529_do_conversion(struct comedi_device *dev,
4797 unsigned short *data)
4798 {
4799 int retval;
4800 unsigned short status;
4801
4802 cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4803 retval = cs5529_wait_for_idle(dev);
4804 if (retval) {
4805 dev_err(dev->class_dev,
4806 "timeout or signal in %s()\n", __func__);
4807 return -ETIME;
4808 }
4809 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4810 if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4811 dev_err(dev->class_dev,
4812 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4813 return -EIO;
4814 }
4815 if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4816 dev_err(dev->class_dev,
4817 "cs5529 conversion error, overrange (ignoring)\n");
4818 }
4819 if (data) {
4820 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4821 /* cs5529 returns 16 bit signed data in bipolar mode */
4822 *data ^= BIT(15);
4823 }
4824 return 0;
4825 }
4826
cs5529_ai_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4827 static int cs5529_ai_insn_read(struct comedi_device *dev,
4828 struct comedi_subdevice *s,
4829 struct comedi_insn *insn,
4830 unsigned int *data)
4831 {
4832 int n, retval;
4833 unsigned short sample;
4834 unsigned int channel_select;
4835 const unsigned int INTERNAL_REF = 0x1000;
4836
4837 /*
4838 * Set calibration adc source. Docs lie, reference select bits 8 to 11
4839 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4840 * 13 causes the adc input to go overrange (maybe reads external
4841 * reference?)
4842 */
4843 if (insn->chanspec & CR_ALT_SOURCE)
4844 channel_select = INTERNAL_REF;
4845 else
4846 channel_select = CR_CHAN(insn->chanspec);
4847 ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4848
4849 for (n = 0; n < insn->n; n++) {
4850 retval = cs5529_do_conversion(dev, &sample);
4851 if (retval < 0)
4852 return retval;
4853 data[n] = sample;
4854 }
4855 return insn->n;
4856 }
4857
cs5529_config_write(struct comedi_device * dev,unsigned int value,unsigned int reg_select_bits)4858 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4859 unsigned int reg_select_bits)
4860 {
4861 ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4862 ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4863 reg_select_bits &= CS5529_CMD_REG_MASK;
4864 cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4865 if (cs5529_wait_for_idle(dev))
4866 dev_err(dev->class_dev,
4867 "timeout or signal in %s\n", __func__);
4868 }
4869
init_cs5529(struct comedi_device * dev)4870 static int init_cs5529(struct comedi_device *dev)
4871 {
4872 unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4873 CS5529_CFG_WORD_RATE_2180;
4874
4875 #if 1
4876 /* do self-calibration */
4877 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4878 CS5529_CFG_REG);
4879 /* need to force a conversion for calibration to run */
4880 cs5529_do_conversion(dev, NULL);
4881 #else
4882 /* force gain calibration to 1 */
4883 cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4884 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4885 CS5529_CFG_REG);
4886 if (cs5529_wait_for_idle(dev))
4887 dev_err(dev->class_dev,
4888 "timeout or signal in %s\n", __func__);
4889 #endif
4890 return 0;
4891 }
4892
4893 /*
4894 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4895 * given an arbitrary frequency input clock.
4896 */
ni_mseries_get_pll_parameters(unsigned int reference_period_ns,unsigned int * freq_divider,unsigned int * freq_multiplier,unsigned int * actual_period_ns)4897 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4898 unsigned int *freq_divider,
4899 unsigned int *freq_multiplier,
4900 unsigned int *actual_period_ns)
4901 {
4902 unsigned int div;
4903 unsigned int best_div = 1;
4904 unsigned int mult;
4905 unsigned int best_mult = 1;
4906 static const unsigned int pico_per_nano = 1000;
4907 const unsigned int reference_picosec = reference_period_ns *
4908 pico_per_nano;
4909 /*
4910 * m-series wants the phased-locked loop to output 80MHz, which is
4911 * divided by 4 to 20 MHz for most timing clocks
4912 */
4913 static const unsigned int target_picosec = 12500;
4914 int best_period_picosec = 0;
4915
4916 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4917 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4918 unsigned int new_period_ps =
4919 (reference_picosec * div) / mult;
4920 if (abs(new_period_ps - target_picosec) <
4921 abs(best_period_picosec - target_picosec)) {
4922 best_period_picosec = new_period_ps;
4923 best_div = div;
4924 best_mult = mult;
4925 }
4926 }
4927 }
4928 if (best_period_picosec == 0)
4929 return -EIO;
4930
4931 *freq_divider = best_div;
4932 *freq_multiplier = best_mult;
4933 /* return the actual period (* fudge factor for 80 to 20 MHz) */
4934 *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4935 pico_per_nano);
4936 return 0;
4937 }
4938
ni_mseries_set_pll_master_clock(struct comedi_device * dev,unsigned int source,unsigned int period_ns)4939 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4940 unsigned int source,
4941 unsigned int period_ns)
4942 {
4943 struct ni_private *devpriv = dev->private;
4944 static const unsigned int min_period_ns = 50;
4945 static const unsigned int max_period_ns = 1000;
4946 static const unsigned int timeout = 1000;
4947 unsigned int pll_control_bits;
4948 unsigned int freq_divider;
4949 unsigned int freq_multiplier;
4950 unsigned int rtsi;
4951 unsigned int i;
4952 int retval;
4953
4954 if (source == NI_MIO_PLL_PXI10_CLOCK)
4955 period_ns = 100;
4956 /*
4957 * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4958 * range so we'll use that.
4959 */
4960 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4961 dev_err(dev->class_dev,
4962 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4963 __func__, min_period_ns, max_period_ns);
4964 return -EINVAL;
4965 }
4966 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4967 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4968 NISTC_RTSI_TRIG_DIR_REG);
4969 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4970 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4971 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4972 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4973 switch (source) {
4974 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4975 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4976 break;
4977 case NI_MIO_PLL_PXI10_CLOCK:
4978 /* pxi clock is 10MHz */
4979 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4980 break;
4981 default:
4982 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4983 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4984 devpriv->clock_and_fout2 |=
4985 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4986 break;
4987 }
4988 }
4989 if (rtsi > NI_M_MAX_RTSI_CHAN)
4990 return -EINVAL;
4991 break;
4992 }
4993 retval = ni_mseries_get_pll_parameters(period_ns,
4994 &freq_divider,
4995 &freq_multiplier,
4996 &devpriv->clock_ns);
4997 if (retval < 0) {
4998 dev_err(dev->class_dev,
4999 "bug, failed to find pll parameters\n");
5000 return retval;
5001 }
5002
5003 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
5004 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
5005 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
5006
5007 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
5008 devpriv->clock_source = source;
5009 /* it takes a few hundred microseconds for PLL to lock */
5010 for (i = 0; i < timeout; ++i) {
5011 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
5012 break;
5013 udelay(1);
5014 }
5015 if (i == timeout) {
5016 dev_err(dev->class_dev,
5017 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
5018 __func__, source, period_ns);
5019 return -ETIMEDOUT;
5020 }
5021 return 3;
5022 }
5023
ni_set_master_clock(struct comedi_device * dev,unsigned int source,unsigned int period_ns)5024 static int ni_set_master_clock(struct comedi_device *dev,
5025 unsigned int source, unsigned int period_ns)
5026 {
5027 struct ni_private *devpriv = dev->private;
5028
5029 if (source == NI_MIO_INTERNAL_CLOCK) {
5030 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
5031 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5032 NISTC_RTSI_TRIG_DIR_REG);
5033 devpriv->clock_ns = TIMEBASE_1_NS;
5034 if (devpriv->is_m_series) {
5035 devpriv->clock_and_fout2 &=
5036 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
5037 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
5038 ni_writew(dev, devpriv->clock_and_fout2,
5039 NI_M_CLK_FOUT2_REG);
5040 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
5041 }
5042 devpriv->clock_source = source;
5043 } else {
5044 if (devpriv->is_m_series) {
5045 return ni_mseries_set_pll_master_clock(dev, source,
5046 period_ns);
5047 } else {
5048 if (source == NI_MIO_RTSI_CLOCK) {
5049 devpriv->rtsi_trig_direction_reg |=
5050 NISTC_RTSI_TRIG_USE_CLK;
5051 ni_stc_writew(dev,
5052 devpriv->rtsi_trig_direction_reg,
5053 NISTC_RTSI_TRIG_DIR_REG);
5054 if (period_ns == 0) {
5055 dev_err(dev->class_dev,
5056 "we don't handle an unspecified clock period correctly yet, returning error\n");
5057 return -EINVAL;
5058 }
5059 devpriv->clock_ns = period_ns;
5060 devpriv->clock_source = source;
5061 } else {
5062 return -EINVAL;
5063 }
5064 }
5065 }
5066 return 3;
5067 }
5068
ni_valid_rtsi_output_source(struct comedi_device * dev,unsigned int chan,unsigned int source)5069 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
5070 unsigned int chan, unsigned int source)
5071 {
5072 struct ni_private *devpriv = dev->private;
5073
5074 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5075 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5076 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5077 return 1;
5078
5079 dev_err(dev->class_dev,
5080 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
5081 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
5082 return 0;
5083 }
5084 return 0;
5085 }
5086 switch (source) {
5087 case NI_RTSI_OUTPUT_ADR_START1:
5088 case NI_RTSI_OUTPUT_ADR_START2:
5089 case NI_RTSI_OUTPUT_SCLKG:
5090 case NI_RTSI_OUTPUT_DACUPDN:
5091 case NI_RTSI_OUTPUT_DA_START1:
5092 case NI_RTSI_OUTPUT_G_SRC0:
5093 case NI_RTSI_OUTPUT_G_GATE0:
5094 case NI_RTSI_OUTPUT_RGOUT0:
5095 case NI_RTSI_OUTPUT_RTSI_BRD(0):
5096 case NI_RTSI_OUTPUT_RTSI_BRD(1):
5097 case NI_RTSI_OUTPUT_RTSI_BRD(2):
5098 case NI_RTSI_OUTPUT_RTSI_BRD(3):
5099 return 1;
5100 case NI_RTSI_OUTPUT_RTSI_OSC:
5101 return (devpriv->is_m_series) ? 1 : 0;
5102 default:
5103 return 0;
5104 }
5105 }
5106
ni_set_rtsi_routing(struct comedi_device * dev,unsigned int chan,unsigned int src)5107 static int ni_set_rtsi_routing(struct comedi_device *dev,
5108 unsigned int chan, unsigned int src)
5109 {
5110 struct ni_private *devpriv = dev->private;
5111
5112 if (chan >= TRIGGER_LINE(0))
5113 /* allow new and old names of rtsi channels to work. */
5114 chan -= TRIGGER_LINE(0);
5115
5116 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5117 return -EINVAL;
5118 if (chan < 4) {
5119 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5120 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5121 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5122 NISTC_RTSI_TRIGA_OUT_REG);
5123 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5124 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5125 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5126 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5127 NISTC_RTSI_TRIGB_OUT_REG);
5128 } else if (chan != NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5129 /* probably should never reach this, since the
5130 * ni_valid_rtsi_output_source above errors out if chan is too
5131 * high
5132 */
5133 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5134 return -EINVAL;
5135 }
5136 return 2;
5137 }
5138
ni_get_rtsi_routing(struct comedi_device * dev,unsigned int chan)5139 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5140 unsigned int chan)
5141 {
5142 struct ni_private *devpriv = dev->private;
5143
5144 if (chan >= TRIGGER_LINE(0))
5145 /* allow new and old names of rtsi channels to work. */
5146 chan -= TRIGGER_LINE(0);
5147
5148 if (chan < 4) {
5149 return NISTC_RTSI_TRIG_TO_SRC(chan,
5150 devpriv->rtsi_trig_a_output_reg);
5151 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5152 return NISTC_RTSI_TRIG_TO_SRC(chan,
5153 devpriv->rtsi_trig_b_output_reg);
5154 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5155 return NI_RTSI_OUTPUT_RTSI_OSC;
5156 }
5157
5158 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5159 return -EINVAL;
5160 }
5161
ni_set_rtsi_direction(struct comedi_device * dev,int chan,unsigned int direction)5162 static void ni_set_rtsi_direction(struct comedi_device *dev, int chan,
5163 unsigned int direction)
5164 {
5165 struct ni_private *devpriv = dev->private;
5166 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5167
5168 if (chan >= TRIGGER_LINE(0))
5169 /* allow new and old names of rtsi channels to work. */
5170 chan -= TRIGGER_LINE(0);
5171
5172 if (direction == COMEDI_OUTPUT) {
5173 if (chan < max_chan) {
5174 devpriv->rtsi_trig_direction_reg |=
5175 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5176 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5177 devpriv->rtsi_trig_direction_reg |=
5178 NISTC_RTSI_TRIG_DRV_CLK;
5179 }
5180 } else {
5181 if (chan < max_chan) {
5182 devpriv->rtsi_trig_direction_reg &=
5183 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5184 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5185 devpriv->rtsi_trig_direction_reg &=
5186 ~NISTC_RTSI_TRIG_DRV_CLK;
5187 }
5188 }
5189 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5190 NISTC_RTSI_TRIG_DIR_REG);
5191 }
5192
ni_get_rtsi_direction(struct comedi_device * dev,int chan)5193 static int ni_get_rtsi_direction(struct comedi_device *dev, int chan)
5194 {
5195 struct ni_private *devpriv = dev->private;
5196 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5197
5198 if (chan >= TRIGGER_LINE(0))
5199 /* allow new and old names of rtsi channels to work. */
5200 chan -= TRIGGER_LINE(0);
5201
5202 if (chan < max_chan) {
5203 return (devpriv->rtsi_trig_direction_reg &
5204 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5205 ? COMEDI_OUTPUT : COMEDI_INPUT;
5206 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5207 return (devpriv->rtsi_trig_direction_reg &
5208 NISTC_RTSI_TRIG_DRV_CLK)
5209 ? COMEDI_OUTPUT : COMEDI_INPUT;
5210 }
5211 return -EINVAL;
5212 }
5213
ni_rtsi_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)5214 static int ni_rtsi_insn_config(struct comedi_device *dev,
5215 struct comedi_subdevice *s,
5216 struct comedi_insn *insn,
5217 unsigned int *data)
5218 {
5219 struct ni_private *devpriv = dev->private;
5220 unsigned int chan = CR_CHAN(insn->chanspec);
5221
5222 switch (data[0]) {
5223 case COMEDI_OUTPUT:
5224 case COMEDI_INPUT:
5225 ni_set_rtsi_direction(dev, chan, data[0]);
5226 break;
5227 case INSN_CONFIG_DIO_QUERY: {
5228 int ret = ni_get_rtsi_direction(dev, chan);
5229
5230 if (ret < 0)
5231 return ret;
5232 data[1] = ret;
5233 return 2;
5234 }
5235 case INSN_CONFIG_SET_CLOCK_SRC:
5236 return ni_set_master_clock(dev, data[1], data[2]);
5237 case INSN_CONFIG_GET_CLOCK_SRC:
5238 data[1] = devpriv->clock_source;
5239 data[2] = devpriv->clock_ns;
5240 return 3;
5241 case INSN_CONFIG_SET_ROUTING:
5242 return ni_set_rtsi_routing(dev, chan, data[1]);
5243 case INSN_CONFIG_GET_ROUTING: {
5244 int ret = ni_get_rtsi_routing(dev, chan);
5245
5246 if (ret < 0)
5247 return ret;
5248 data[1] = ret;
5249 return 2;
5250 }
5251 default:
5252 return -EINVAL;
5253 }
5254 return 1;
5255 }
5256
ni_rtsi_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)5257 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5258 struct comedi_subdevice *s,
5259 struct comedi_insn *insn,
5260 unsigned int *data)
5261 {
5262 data[1] = 0;
5263
5264 return insn->n;
5265 }
5266
5267 /*
5268 * Default routing for RTSI trigger lines.
5269 *
5270 * These values are used here in the init function, as well as in the
5271 * disconnect_route function, after a RTSI route has been disconnected.
5272 */
5273 static const int default_rtsi_routing[] = {
5274 [0] = NI_RTSI_OUTPUT_ADR_START1,
5275 [1] = NI_RTSI_OUTPUT_ADR_START2,
5276 [2] = NI_RTSI_OUTPUT_SCLKG,
5277 [3] = NI_RTSI_OUTPUT_DACUPDN,
5278 [4] = NI_RTSI_OUTPUT_DA_START1,
5279 [5] = NI_RTSI_OUTPUT_G_SRC0,
5280 [6] = NI_RTSI_OUTPUT_G_GATE0,
5281 [7] = NI_RTSI_OUTPUT_RTSI_OSC,
5282 };
5283
5284 /*
5285 * Route signals through RGOUT0 terminal.
5286 * @reg: raw register value of RGOUT0 bits (only bit0 is important).
5287 * @dev: comedi device handle.
5288 */
set_rgout0_reg(int reg,struct comedi_device * dev)5289 static void set_rgout0_reg(int reg, struct comedi_device *dev)
5290 {
5291 struct ni_private *devpriv = dev->private;
5292
5293 if (devpriv->is_m_series) {
5294 devpriv->rtsi_trig_direction_reg &=
5295 ~NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5296 devpriv->rtsi_trig_direction_reg |=
5297 (reg << NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT) &
5298 NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5299 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5300 NISTC_RTSI_TRIG_DIR_REG);
5301 } else {
5302 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIGB_SUB_SEL1;
5303 devpriv->rtsi_trig_b_output_reg |=
5304 (reg << NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT) &
5305 NISTC_RTSI_TRIGB_SUB_SEL1;
5306 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5307 NISTC_RTSI_TRIGB_OUT_REG);
5308 }
5309 }
5310
get_rgout0_reg(struct comedi_device * dev)5311 static int get_rgout0_reg(struct comedi_device *dev)
5312 {
5313 struct ni_private *devpriv = dev->private;
5314 int reg;
5315
5316 if (devpriv->is_m_series)
5317 reg = (devpriv->rtsi_trig_direction_reg &
5318 NISTC_RTSI_TRIG_DIR_SUB_SEL1)
5319 >> NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT;
5320 else
5321 reg = (devpriv->rtsi_trig_b_output_reg &
5322 NISTC_RTSI_TRIGB_SUB_SEL1)
5323 >> NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT;
5324 return reg;
5325 }
5326
get_rgout0_src(struct comedi_device * dev)5327 static inline int get_rgout0_src(struct comedi_device *dev)
5328 {
5329 struct ni_private *devpriv = dev->private;
5330 int reg = get_rgout0_reg(dev);
5331
5332 return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables);
5333 }
5334
5335 /*
5336 * Route signals through RGOUT0 terminal and increment the RGOUT0 use for this
5337 * particular route.
5338 * @src: device-global signal name
5339 * @dev: comedi device handle
5340 *
5341 * Return: -EINVAL if the source is not valid to route to RGOUT0;
5342 * -EBUSY if the RGOUT0 is already used;
5343 * 0 if successful.
5344 */
incr_rgout0_src_use(int src,struct comedi_device * dev)5345 static int incr_rgout0_src_use(int src, struct comedi_device *dev)
5346 {
5347 struct ni_private *devpriv = dev->private;
5348 s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5349 &devpriv->routing_tables);
5350
5351 if (reg < 0)
5352 return -EINVAL;
5353
5354 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg)
5355 return -EBUSY;
5356
5357 ++devpriv->rgout0_usage;
5358 set_rgout0_reg(reg, dev);
5359 return 0;
5360 }
5361
5362 /*
5363 * Unroute signals through RGOUT0 terminal and deccrement the RGOUT0 use for
5364 * this particular source. This function does not actually unroute anything
5365 * with respect to RGOUT0. It does, on the other hand, decrement the usage
5366 * counter for the current src->RGOUT0 mapping.
5367 *
5368 * Return: -EINVAL if the source is not already routed to RGOUT0 (or usage is
5369 * already at zero); 0 if successful.
5370 */
decr_rgout0_src_use(int src,struct comedi_device * dev)5371 static int decr_rgout0_src_use(int src, struct comedi_device *dev)
5372 {
5373 struct ni_private *devpriv = dev->private;
5374 s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5375 &devpriv->routing_tables);
5376
5377 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) {
5378 --devpriv->rgout0_usage;
5379 if (!devpriv->rgout0_usage)
5380 set_rgout0_reg(0, dev); /* ok default? */
5381 return 0;
5382 }
5383 return -EINVAL;
5384 }
5385
5386 /*
5387 * Route signals through given NI_RTSI_BRD mux.
5388 * @i: index of mux to route
5389 * @reg: raw register value of RTSI_BRD bits
5390 * @dev: comedi device handle
5391 */
set_ith_rtsi_brd_reg(int i,int reg,struct comedi_device * dev)5392 static void set_ith_rtsi_brd_reg(int i, int reg, struct comedi_device *dev)
5393 {
5394 struct ni_private *devpriv = dev->private;
5395 int reg_i_sz = 3; /* value for e-series */
5396 int reg_i_mask;
5397 int reg_i_shift;
5398
5399 if (devpriv->is_m_series)
5400 reg_i_sz = 4;
5401 reg_i_mask = ~((~0) << reg_i_sz);
5402 reg_i_shift = i * reg_i_sz;
5403
5404 /* clear out the current reg_i for ith brd */
5405 devpriv->rtsi_shared_mux_reg &= ~(reg_i_mask << reg_i_shift);
5406 /* (softcopy) write the new reg_i for ith brd */
5407 devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift;
5408 /* (hardcopy) write the new reg_i for ith brd */
5409 ni_stc_writew(dev, devpriv->rtsi_shared_mux_reg, NISTC_RTSI_BOARD_REG);
5410 }
5411
get_ith_rtsi_brd_reg(int i,struct comedi_device * dev)5412 static int get_ith_rtsi_brd_reg(int i, struct comedi_device *dev)
5413 {
5414 struct ni_private *devpriv = dev->private;
5415 int reg_i_sz = 3; /* value for e-series */
5416 int reg_i_mask;
5417 int reg_i_shift;
5418
5419 if (devpriv->is_m_series)
5420 reg_i_sz = 4;
5421 reg_i_mask = ~((~0) << reg_i_sz);
5422 reg_i_shift = i * reg_i_sz;
5423
5424 return (devpriv->rtsi_shared_mux_reg >> reg_i_shift) & reg_i_mask;
5425 }
5426
get_rtsi_brd_src(int brd,struct comedi_device * dev)5427 static inline int get_rtsi_brd_src(int brd, struct comedi_device *dev)
5428 {
5429 struct ni_private *devpriv = dev->private;
5430 int brd_index = brd;
5431 int reg;
5432
5433 if (brd >= NI_RTSI_BRD(0))
5434 brd_index = brd - NI_RTSI_BRD(0);
5435 else
5436 brd = NI_RTSI_BRD(brd);
5437 /*
5438 * And now:
5439 * brd : device-global name
5440 * brd_index : index number of RTSI_BRD mux
5441 */
5442
5443 reg = get_ith_rtsi_brd_reg(brd_index, dev);
5444
5445 return ni_find_route_source(reg, brd, &devpriv->routing_tables);
5446 }
5447
5448 /*
5449 * Route signals through NI_RTSI_BRD mux and increment the use counter for this
5450 * particular route.
5451 *
5452 * Return: -EINVAL if the source is not valid to route to NI_RTSI_BRD(i);
5453 * -EBUSY if all NI_RTSI_BRD muxes are already used;
5454 * NI_RTSI_BRD(i) of allocated ith mux if successful.
5455 */
incr_rtsi_brd_src_use(int src,struct comedi_device * dev)5456 static int incr_rtsi_brd_src_use(int src, struct comedi_device *dev)
5457 {
5458 struct ni_private *devpriv = dev->private;
5459 int first_available = -1;
5460 int err = -EINVAL;
5461 s8 reg;
5462 int i;
5463
5464 /* first look for a mux that is already configured to provide src */
5465 for (i = 0; i < NUM_RTSI_SHARED_MUXS; ++i) {
5466 reg = ni_lookup_route_register(CR_CHAN(src), NI_RTSI_BRD(i),
5467 &devpriv->routing_tables);
5468
5469 if (reg < 0)
5470 continue; /* invalid route */
5471
5472 if (!devpriv->rtsi_shared_mux_usage[i]) {
5473 if (first_available < 0)
5474 /* found the first unused, but usable mux */
5475 first_available = i;
5476 } else {
5477 /*
5478 * we've seen at least one possible route, so change the
5479 * final error to -EBUSY in case there are no muxes
5480 * available.
5481 */
5482 err = -EBUSY;
5483
5484 if (get_ith_rtsi_brd_reg(i, dev) == reg) {
5485 /*
5486 * we've found a mux that is already being used
5487 * to provide the requested signal. Reuse it.
5488 */
5489 goto success;
5490 }
5491 }
5492 }
5493
5494 if (first_available < 0)
5495 return err;
5496
5497 /* we did not find a mux to reuse, but there is at least one usable */
5498 i = first_available;
5499
5500 success:
5501 ++devpriv->rtsi_shared_mux_usage[i];
5502 set_ith_rtsi_brd_reg(i, reg, dev);
5503 return NI_RTSI_BRD(i);
5504 }
5505
5506 /*
5507 * Unroute signals through NI_RTSI_BRD mux and decrement the user counter for
5508 * this particular route.
5509 *
5510 * Return: -EINVAL if the source is not already routed to rtsi_brd(i) (or usage
5511 * is already at zero); 0 if successful.
5512 */
decr_rtsi_brd_src_use(int src,int rtsi_brd,struct comedi_device * dev)5513 static int decr_rtsi_brd_src_use(int src, int rtsi_brd,
5514 struct comedi_device *dev)
5515 {
5516 struct ni_private *devpriv = dev->private;
5517 s8 reg = ni_lookup_route_register(CR_CHAN(src), rtsi_brd,
5518 &devpriv->routing_tables);
5519 const int i = rtsi_brd - NI_RTSI_BRD(0);
5520
5521 if (devpriv->rtsi_shared_mux_usage[i] > 0 &&
5522 get_ith_rtsi_brd_reg(i, dev) == reg) {
5523 --devpriv->rtsi_shared_mux_usage[i];
5524 if (!devpriv->rtsi_shared_mux_usage[i])
5525 set_ith_rtsi_brd_reg(i, 0, dev); /* ok default? */
5526 return 0;
5527 }
5528
5529 return -EINVAL;
5530 }
5531
ni_rtsi_init(struct comedi_device * dev)5532 static void ni_rtsi_init(struct comedi_device *dev)
5533 {
5534 struct ni_private *devpriv = dev->private;
5535 int i;
5536
5537 /* Initialises the RTSI bus signal switch to a default state */
5538
5539 /*
5540 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5541 * to have no effect, at least on pxi-6281, which always uses
5542 * 20MHz rtsi clock frequency
5543 */
5544 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5545 /* Set clock mode to internal */
5546 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5547 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5548
5549 /* default internal lines routing to RTSI bus lines */
5550 for (i = 0; i < 8; ++i) {
5551 ni_set_rtsi_direction(dev, i, COMEDI_INPUT);
5552 ni_set_rtsi_routing(dev, i, default_rtsi_routing[i]);
5553 }
5554
5555 /*
5556 * Sets the source and direction of the 4 on board lines.
5557 * This configures all board lines to be:
5558 * for e-series:
5559 * 1) inputs (not sure what "output" would mean)
5560 * 2) copying TRIGGER_LINE(0) (or RTSI0) output
5561 * for m-series:
5562 * copying NI_PFI(0) output
5563 */
5564 devpriv->rtsi_shared_mux_reg = 0;
5565 for (i = 0; i < 4; ++i)
5566 set_ith_rtsi_brd_reg(i, 0, dev);
5567 memset(devpriv->rtsi_shared_mux_usage, 0,
5568 sizeof(devpriv->rtsi_shared_mux_usage));
5569
5570 /* initialize rgout0 pin as unused. */
5571 devpriv->rgout0_usage = 0;
5572 set_rgout0_reg(0, dev);
5573 }
5574
5575 /* Get route of GPFO_i/CtrOut pins */
ni_get_gout_routing(unsigned int dest,struct comedi_device * dev)5576 static inline int ni_get_gout_routing(unsigned int dest,
5577 struct comedi_device *dev)
5578 {
5579 struct ni_private *devpriv = dev->private;
5580 unsigned int reg = devpriv->an_trig_etc_reg;
5581
5582 switch (dest) {
5583 case 0:
5584 if (reg & NISTC_ATRIG_ETC_GPFO_0_ENA)
5585 return NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(reg);
5586 break;
5587 case 1:
5588 if (reg & NISTC_ATRIG_ETC_GPFO_1_ENA)
5589 return NISTC_ATRIG_ETC_GPFO_1_SEL_TO_SRC(reg);
5590 break;
5591 }
5592
5593 return -EINVAL;
5594 }
5595
5596 /* Set route of GPFO_i/CtrOut pins */
ni_disable_gout_routing(unsigned int dest,struct comedi_device * dev)5597 static inline int ni_disable_gout_routing(unsigned int dest,
5598 struct comedi_device *dev)
5599 {
5600 struct ni_private *devpriv = dev->private;
5601
5602 switch (dest) {
5603 case 0:
5604 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_ENA;
5605 break;
5606 case 1:
5607 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_ENA;
5608 break;
5609 default:
5610 return -EINVAL;
5611 }
5612
5613 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5614 return 0;
5615 }
5616
5617 /* Set route of GPFO_i/CtrOut pins */
ni_set_gout_routing(unsigned int src,unsigned int dest,struct comedi_device * dev)5618 static inline int ni_set_gout_routing(unsigned int src, unsigned int dest,
5619 struct comedi_device *dev)
5620 {
5621 struct ni_private *devpriv = dev->private;
5622
5623 switch (dest) {
5624 case 0:
5625 /* clear reg */
5626 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_SEL(-1);
5627 /* set reg */
5628 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_0_ENA
5629 | NISTC_ATRIG_ETC_GPFO_0_SEL(src);
5630 break;
5631 case 1:
5632 /* clear reg */
5633 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_SEL;
5634 src = src ? NISTC_ATRIG_ETC_GPFO_1_SEL : 0;
5635 /* set reg */
5636 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_1_ENA | src;
5637 break;
5638 default:
5639 return -EINVAL;
5640 }
5641
5642 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5643 return 0;
5644 }
5645
5646 /*
5647 * Retrieves the current source of the output selector for the given
5648 * destination. If the terminal for the destination is not already configured
5649 * as an output, this function returns -EINVAL as error.
5650 *
5651 * Return: the register value of the destination output selector;
5652 * -EINVAL if terminal is not configured for output.
5653 */
get_output_select_source(int dest,struct comedi_device * dev)5654 static int get_output_select_source(int dest, struct comedi_device *dev)
5655 {
5656 struct ni_private *devpriv = dev->private;
5657 int reg = -1;
5658
5659 if (channel_is_pfi(dest)) {
5660 if (ni_get_pfi_direction(dev, dest) == COMEDI_OUTPUT)
5661 reg = ni_get_pfi_routing(dev, dest);
5662 } else if (channel_is_rtsi(dest)) {
5663 if (ni_get_rtsi_direction(dev, dest) == COMEDI_OUTPUT) {
5664 reg = ni_get_rtsi_routing(dev, dest);
5665
5666 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5667 dest = NI_RGOUT0; /* prepare for lookup below */
5668 reg = get_rgout0_reg(dev);
5669 } else if (reg >= NI_RTSI_OUTPUT_RTSI_BRD(0) &&
5670 reg <= NI_RTSI_OUTPUT_RTSI_BRD(3)) {
5671 const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0);
5672
5673 dest = NI_RTSI_BRD(i); /* prepare for lookup */
5674 reg = get_ith_rtsi_brd_reg(i, dev);
5675 }
5676 }
5677 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5678 /*
5679 * not handled by ni_tio. Only available for GPFO registers in
5680 * e/m series.
5681 */
5682 dest -= NI_CtrOut(0);
5683 if (dest > 1)
5684 /* there are only two g_out outputs. */
5685 return -EINVAL;
5686 reg = ni_get_gout_routing(dest, dev);
5687 } else if (channel_is_ctr(dest)) {
5688 reg = ni_tio_get_routing(devpriv->counter_dev, dest);
5689 } else {
5690 dev_dbg(dev->class_dev, "%s: unhandled destination (%d) queried\n",
5691 __func__, dest);
5692 }
5693
5694 if (reg >= 0)
5695 return ni_find_route_source(CR_CHAN(reg), dest,
5696 &devpriv->routing_tables);
5697 return -EINVAL;
5698 }
5699
5700 /*
5701 * Test a route:
5702 *
5703 * Return: -1 if not connectible;
5704 * 0 if connectible and not connected;
5705 * 1 if connectible and connected.
5706 */
test_route(unsigned int src,unsigned int dest,struct comedi_device * dev)5707 static int test_route(unsigned int src, unsigned int dest,
5708 struct comedi_device *dev)
5709 {
5710 struct ni_private *devpriv = dev->private;
5711 s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5712 &devpriv->routing_tables);
5713
5714 if (reg < 0)
5715 return -1;
5716 if (get_output_select_source(dest, dev) != CR_CHAN(src))
5717 return 0;
5718 return 1;
5719 }
5720
5721 /* Connect the actual route. */
connect_route(unsigned int src,unsigned int dest,struct comedi_device * dev)5722 static int connect_route(unsigned int src, unsigned int dest,
5723 struct comedi_device *dev)
5724 {
5725 struct ni_private *devpriv = dev->private;
5726 s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5727 &devpriv->routing_tables);
5728 s8 current_src;
5729
5730 if (reg < 0)
5731 /* route is not valid */
5732 return -EINVAL;
5733
5734 current_src = get_output_select_source(dest, dev);
5735 if (current_src == CR_CHAN(src))
5736 return -EALREADY;
5737 if (current_src >= 0)
5738 /* destination mux is already busy. complain, don't overwrite */
5739 return -EBUSY;
5740
5741 /* The route is valid and available. Now connect... */
5742 if (channel_is_pfi(dest)) {
5743 /* set routing source, then open output */
5744 ni_set_pfi_routing(dev, dest, reg);
5745 ni_set_pfi_direction(dev, dest, COMEDI_OUTPUT);
5746 } else if (channel_is_rtsi(dest)) {
5747 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5748 int ret = incr_rgout0_src_use(src, dev);
5749
5750 if (ret < 0)
5751 return ret;
5752 } else if (ni_rtsi_route_requires_mux(reg)) {
5753 /* Attempt to allocate and route (src->brd) */
5754 int brd = incr_rtsi_brd_src_use(src, dev);
5755
5756 if (brd < 0)
5757 return brd;
5758
5759 /* Now lookup the register value for (brd->dest) */
5760 reg = ni_lookup_route_register(
5761 brd, dest, &devpriv->routing_tables);
5762 }
5763
5764 ni_set_rtsi_direction(dev, dest, COMEDI_OUTPUT);
5765 ni_set_rtsi_routing(dev, dest, reg);
5766 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5767 /*
5768 * not handled by ni_tio. Only available for GPFO registers in
5769 * e/m series.
5770 */
5771 dest -= NI_CtrOut(0);
5772 if (dest > 1)
5773 /* there are only two g_out outputs. */
5774 return -EINVAL;
5775 if (ni_set_gout_routing(src, dest, dev))
5776 return -EINVAL;
5777 } else if (channel_is_ctr(dest)) {
5778 /*
5779 * we are adding back the channel modifier info to set
5780 * invert/edge info passed by the user
5781 */
5782 ni_tio_set_routing(devpriv->counter_dev, dest,
5783 reg | (src & ~CR_CHAN(-1)));
5784 } else {
5785 return -EINVAL;
5786 }
5787 return 0;
5788 }
5789
disconnect_route(unsigned int src,unsigned int dest,struct comedi_device * dev)5790 static int disconnect_route(unsigned int src, unsigned int dest,
5791 struct comedi_device *dev)
5792 {
5793 struct ni_private *devpriv = dev->private;
5794 s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5795 &devpriv->routing_tables);
5796
5797 if (reg < 0)
5798 /* route is not valid */
5799 return -EINVAL;
5800 if (get_output_select_source(dest, dev) != src)
5801 /* cannot disconnect something not connected */
5802 return -EINVAL;
5803
5804 /* The route is valid and is connected. Now disconnect... */
5805 if (channel_is_pfi(dest)) {
5806 /* set the pfi to high impedance, and disconnect */
5807 ni_set_pfi_direction(dev, dest, COMEDI_INPUT);
5808 ni_set_pfi_routing(dev, dest, NI_PFI_OUTPUT_PFI_DEFAULT);
5809 } else if (channel_is_rtsi(dest)) {
5810 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5811 int ret = decr_rgout0_src_use(src, dev);
5812
5813 if (ret < 0)
5814 return ret;
5815 } else if (ni_rtsi_route_requires_mux(reg)) {
5816 /* find which RTSI_BRD line is source for rtsi pin */
5817 int brd = ni_find_route_source(
5818 ni_get_rtsi_routing(dev, dest), dest,
5819 &devpriv->routing_tables);
5820
5821 if (brd < 0)
5822 return brd;
5823
5824 /* decrement/disconnect RTSI_BRD line from source */
5825 decr_rtsi_brd_src_use(src, brd, dev);
5826 }
5827
5828 /* set rtsi output selector to default state */
5829 reg = default_rtsi_routing[dest - TRIGGER_LINE(0)];
5830 ni_set_rtsi_direction(dev, dest, COMEDI_INPUT);
5831 ni_set_rtsi_routing(dev, dest, reg);
5832 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5833 /*
5834 * not handled by ni_tio. Only available for GPFO registers in
5835 * e/m series.
5836 */
5837 dest -= NI_CtrOut(0);
5838 if (dest > 1)
5839 /* there are only two g_out outputs. */
5840 return -EINVAL;
5841 reg = ni_disable_gout_routing(dest, dev);
5842 } else if (channel_is_ctr(dest)) {
5843 ni_tio_unset_routing(devpriv->counter_dev, dest);
5844 } else {
5845 return -EINVAL;
5846 }
5847 return 0;
5848 }
5849
ni_global_insn_config(struct comedi_device * dev,struct comedi_insn * insn,unsigned int * data)5850 static int ni_global_insn_config(struct comedi_device *dev,
5851 struct comedi_insn *insn,
5852 unsigned int *data)
5853 {
5854 switch (data[0]) {
5855 case INSN_DEVICE_CONFIG_TEST_ROUTE:
5856 data[0] = test_route(data[1], data[2], dev);
5857 return 2;
5858 case INSN_DEVICE_CONFIG_CONNECT_ROUTE:
5859 return connect_route(data[1], data[2], dev);
5860 case INSN_DEVICE_CONFIG_DISCONNECT_ROUTE:
5861 return disconnect_route(data[1], data[2], dev);
5862 /*
5863 * This case is already handled one level up.
5864 * case INSN_DEVICE_CONFIG_GET_ROUTES:
5865 */
5866 default:
5867 return -EINVAL;
5868 }
5869 return 1;
5870 }
5871
5872 #ifdef PCIDMA
ni_gpct_cmd(struct comedi_device * dev,struct comedi_subdevice * s)5873 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5874 {
5875 struct ni_gpct *counter = s->private;
5876 int retval;
5877
5878 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5879 COMEDI_INPUT);
5880 if (retval) {
5881 dev_err(dev->class_dev,
5882 "no dma channel available for use by counter\n");
5883 return retval;
5884 }
5885 ni_tio_acknowledge(counter);
5886 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5887
5888 return ni_tio_cmd(dev, s);
5889 }
5890
ni_gpct_cancel(struct comedi_device * dev,struct comedi_subdevice * s)5891 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5892 {
5893 struct ni_gpct *counter = s->private;
5894 int retval;
5895
5896 retval = ni_tio_cancel(counter);
5897 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5898 ni_release_gpct_mite_channel(dev, counter->counter_index);
5899 return retval;
5900 }
5901 #endif
5902
ni_E_interrupt(int irq,void * d)5903 static irqreturn_t ni_E_interrupt(int irq, void *d)
5904 {
5905 struct comedi_device *dev = d;
5906 struct comedi_subdevice *s_ai = dev->read_subdev;
5907 struct comedi_subdevice *s_ao = dev->write_subdev;
5908 unsigned short a_status;
5909 unsigned short b_status;
5910 unsigned long flags;
5911 #ifdef PCIDMA
5912 struct ni_private *devpriv = dev->private;
5913 #endif
5914
5915 if (!dev->attached)
5916 return IRQ_NONE;
5917 smp_mb(); /* make sure dev->attached is checked */
5918
5919 /* lock to avoid race with comedi_poll */
5920 spin_lock_irqsave(&dev->spinlock, flags);
5921 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5922 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5923 #ifdef PCIDMA
5924 if (devpriv->mite) {
5925 unsigned long flags_too;
5926
5927 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5928 if (s_ai && devpriv->ai_mite_chan)
5929 mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5930 if (s_ao && devpriv->ao_mite_chan)
5931 mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5932 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5933 }
5934 #endif
5935 ack_a_interrupt(dev, a_status);
5936 ack_b_interrupt(dev, b_status);
5937 if (s_ai) {
5938 if (a_status & NISTC_AI_STATUS1_INTA)
5939 handle_a_interrupt(dev, s_ai, a_status);
5940 /* handle any interrupt or dma events */
5941 comedi_handle_events(dev, s_ai);
5942 }
5943 if (s_ao) {
5944 if (b_status & NISTC_AO_STATUS1_INTB)
5945 handle_b_interrupt(dev, s_ao, b_status);
5946 /* handle any interrupt or dma events */
5947 comedi_handle_events(dev, s_ao);
5948 }
5949 handle_gpct_interrupt(dev, 0);
5950 handle_gpct_interrupt(dev, 1);
5951 #ifdef PCIDMA
5952 if (devpriv->is_m_series)
5953 handle_cdio_interrupt(dev);
5954 #endif
5955
5956 spin_unlock_irqrestore(&dev->spinlock, flags);
5957 return IRQ_HANDLED;
5958 }
5959
ni_alloc_private(struct comedi_device * dev)5960 static int ni_alloc_private(struct comedi_device *dev)
5961 {
5962 struct ni_private *devpriv;
5963
5964 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5965 if (!devpriv)
5966 return -ENOMEM;
5967
5968 spin_lock_init(&devpriv->window_lock);
5969 spin_lock_init(&devpriv->soft_reg_copy_lock);
5970 spin_lock_init(&devpriv->mite_channel_lock);
5971
5972 return 0;
5973 }
5974
_ni_get_valid_routes(struct comedi_device * dev,unsigned int n_pairs,unsigned int * pair_data)5975 static unsigned int _ni_get_valid_routes(struct comedi_device *dev,
5976 unsigned int n_pairs,
5977 unsigned int *pair_data)
5978 {
5979 struct ni_private *devpriv = dev->private;
5980
5981 return ni_get_valid_routes(&devpriv->routing_tables, n_pairs,
5982 pair_data);
5983 }
5984
ni_E_init(struct comedi_device * dev,unsigned int interrupt_pin,unsigned int irq_polarity)5985 static int ni_E_init(struct comedi_device *dev,
5986 unsigned int interrupt_pin, unsigned int irq_polarity)
5987 {
5988 const struct ni_board_struct *board = dev->board_ptr;
5989 struct ni_private *devpriv = dev->private;
5990 struct comedi_subdevice *s;
5991 int ret;
5992 int i;
5993 const char *dev_family = devpriv->is_m_series ? "ni_mseries"
5994 : "ni_eseries";
5995 if (!IS_PCIMIO != !dev->mmio) {
5996 dev_err(dev->class_dev,
5997 "%s: bug! %s device not supported.\n",
5998 KBUILD_MODNAME, board->name);
5999 return -ENXIO;
6000 }
6001
6002 /* prepare the device for globally-named routes. */
6003 if (ni_assign_device_routes(dev_family, board->name,
6004 board->alt_route_name,
6005 &devpriv->routing_tables) < 0) {
6006 dev_warn(dev->class_dev, "%s: %s device has no signal routing table.\n",
6007 __func__, board->name);
6008 dev_warn(dev->class_dev, "%s: High level NI signal names will not be available for this %s board.\n",
6009 __func__, board->name);
6010 } else {
6011 /*
6012 * only(?) assign insn_device_config if we have global names for
6013 * this device.
6014 */
6015 dev->insn_device_config = ni_global_insn_config;
6016 dev->get_valid_routes = _ni_get_valid_routes;
6017 }
6018
6019 if (board->n_aochan > MAX_N_AO_CHAN) {
6020 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
6021 return -EINVAL;
6022 }
6023
6024 /* initialize clock dividers */
6025 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
6026 NISTC_CLK_FOUT_SLOW_TIMEBASE |
6027 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
6028 NISTC_CLK_FOUT_TO_BOARD;
6029 if (!devpriv->is_6xxx) {
6030 /* BEAM is this needed for PCI-6143 ?? */
6031 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
6032 NISTC_CLK_FOUT_AO_OUT_DIV2);
6033 }
6034 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
6035
6036 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
6037 if (ret)
6038 return ret;
6039
6040 /* Analog Input subdevice */
6041 s = &dev->subdevices[NI_AI_SUBDEV];
6042 if (board->n_adchan) {
6043 s->type = COMEDI_SUBD_AI;
6044 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
6045 if (!devpriv->is_611x)
6046 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
6047 if (board->ai_maxdata > 0xffff)
6048 s->subdev_flags |= SDF_LSAMPL;
6049 if (devpriv->is_m_series)
6050 s->subdev_flags |= SDF_SOFT_CALIBRATED;
6051 s->n_chan = board->n_adchan;
6052 s->maxdata = board->ai_maxdata;
6053 s->range_table = ni_range_lkup[board->gainlkup];
6054 s->insn_read = ni_ai_insn_read;
6055 s->insn_config = ni_ai_insn_config;
6056 if (dev->irq) {
6057 dev->read_subdev = s;
6058 s->subdev_flags |= SDF_CMD_READ;
6059 s->len_chanlist = 512;
6060 s->do_cmdtest = ni_ai_cmdtest;
6061 s->do_cmd = ni_ai_cmd;
6062 s->cancel = ni_ai_reset;
6063 s->poll = ni_ai_poll;
6064 s->munge = ni_ai_munge;
6065
6066 if (devpriv->mite)
6067 s->async_dma_dir = DMA_FROM_DEVICE;
6068 }
6069
6070 /* reset the analog input configuration */
6071 ni_ai_reset(dev, s);
6072 } else {
6073 s->type = COMEDI_SUBD_UNUSED;
6074 }
6075
6076 /* Analog Output subdevice */
6077 s = &dev->subdevices[NI_AO_SUBDEV];
6078 if (board->n_aochan) {
6079 s->type = COMEDI_SUBD_AO;
6080 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
6081 if (devpriv->is_m_series)
6082 s->subdev_flags |= SDF_SOFT_CALIBRATED;
6083 s->n_chan = board->n_aochan;
6084 s->maxdata = board->ao_maxdata;
6085 s->range_table = board->ao_range_table;
6086 s->insn_config = ni_ao_insn_config;
6087 s->insn_write = ni_ao_insn_write;
6088
6089 ret = comedi_alloc_subdev_readback(s);
6090 if (ret)
6091 return ret;
6092
6093 /*
6094 * Along with the IRQ we need either a FIFO or DMA for
6095 * async command support.
6096 */
6097 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
6098 dev->write_subdev = s;
6099 s->subdev_flags |= SDF_CMD_WRITE;
6100 s->len_chanlist = s->n_chan;
6101 s->do_cmdtest = ni_ao_cmdtest;
6102 s->do_cmd = ni_ao_cmd;
6103 s->cancel = ni_ao_reset;
6104 if (!devpriv->is_m_series)
6105 s->munge = ni_ao_munge;
6106
6107 if (devpriv->mite)
6108 s->async_dma_dir = DMA_TO_DEVICE;
6109 }
6110
6111 if (devpriv->is_67xx)
6112 init_ao_67xx(dev, s);
6113
6114 /* reset the analog output configuration */
6115 ni_ao_reset(dev, s);
6116 } else {
6117 s->type = COMEDI_SUBD_UNUSED;
6118 }
6119
6120 /* Digital I/O subdevice */
6121 s = &dev->subdevices[NI_DIO_SUBDEV];
6122 s->type = COMEDI_SUBD_DIO;
6123 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
6124 s->n_chan = board->has_32dio_chan ? 32 : 8;
6125 s->maxdata = 1;
6126 s->range_table = &range_digital;
6127 if (devpriv->is_m_series) {
6128 #ifdef PCIDMA
6129 s->subdev_flags |= SDF_LSAMPL;
6130 s->insn_bits = ni_m_series_dio_insn_bits;
6131 s->insn_config = ni_m_series_dio_insn_config;
6132 if (dev->irq) {
6133 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
6134 s->len_chanlist = s->n_chan;
6135 s->do_cmdtest = ni_cdio_cmdtest;
6136 s->do_cmd = ni_cdio_cmd;
6137 s->cancel = ni_cdio_cancel;
6138
6139 /* M-series boards use DMA */
6140 s->async_dma_dir = DMA_BIDIRECTIONAL;
6141 }
6142
6143 /* reset DIO and set all channels to inputs */
6144 ni_writel(dev, NI_M_CDO_CMD_RESET |
6145 NI_M_CDI_CMD_RESET,
6146 NI_M_CDIO_CMD_REG);
6147 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
6148 #endif /* PCIDMA */
6149 } else {
6150 s->insn_bits = ni_dio_insn_bits;
6151 s->insn_config = ni_dio_insn_config;
6152
6153 /* set all channels to inputs */
6154 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
6155 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
6156 }
6157
6158 /* 8255 device */
6159 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
6160 if (board->has_8255) {
6161 ret = subdev_8255_cb_init(dev, s, ni_8255_callback,
6162 NI_E_8255_BASE);
6163 if (ret)
6164 return ret;
6165 } else {
6166 s->type = COMEDI_SUBD_UNUSED;
6167 }
6168
6169 /* formerly general purpose counter/timer device, but no longer used */
6170 s = &dev->subdevices[NI_UNUSED_SUBDEV];
6171 s->type = COMEDI_SUBD_UNUSED;
6172
6173 /* Calibration subdevice */
6174 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
6175 s->type = COMEDI_SUBD_CALIB;
6176 s->subdev_flags = SDF_INTERNAL;
6177 s->n_chan = 1;
6178 s->maxdata = 0;
6179 if (devpriv->is_m_series) {
6180 /* internal PWM output used for AI nonlinearity calibration */
6181 s->insn_config = ni_m_series_pwm_config;
6182
6183 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
6184 } else if (devpriv->is_6143) {
6185 /* internal PWM output used for AI nonlinearity calibration */
6186 s->insn_config = ni_6143_pwm_config;
6187 } else {
6188 s->subdev_flags |= SDF_WRITABLE;
6189 s->insn_read = ni_calib_insn_read;
6190 s->insn_write = ni_calib_insn_write;
6191
6192 /* setup the caldacs and find the real n_chan and maxdata */
6193 caldac_setup(dev, s);
6194 }
6195
6196 /* EEPROM subdevice */
6197 s = &dev->subdevices[NI_EEPROM_SUBDEV];
6198 s->type = COMEDI_SUBD_MEMORY;
6199 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
6200 s->maxdata = 0xff;
6201 if (devpriv->is_m_series) {
6202 s->n_chan = M_SERIES_EEPROM_SIZE;
6203 s->insn_read = ni_m_series_eeprom_insn_read;
6204 } else {
6205 s->n_chan = 512;
6206 s->insn_read = ni_eeprom_insn_read;
6207 }
6208
6209 /* Digital I/O (PFI) subdevice */
6210 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
6211 s->type = COMEDI_SUBD_DIO;
6212 s->maxdata = 1;
6213 if (devpriv->is_m_series) {
6214 s->n_chan = 16;
6215 s->insn_bits = ni_pfi_insn_bits;
6216 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6217
6218 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
6219 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
6220 ni_writew(dev, devpriv->pfi_output_select_reg[i],
6221 NI_M_PFI_OUT_SEL_REG(i));
6222 }
6223 } else {
6224 s->n_chan = 10;
6225 s->subdev_flags = SDF_INTERNAL;
6226 }
6227 s->insn_config = ni_pfi_insn_config;
6228
6229 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
6230
6231 /* cs5529 calibration adc */
6232 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
6233 if (devpriv->is_67xx) {
6234 s->type = COMEDI_SUBD_AI;
6235 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
6236 /* one channel for each analog output channel */
6237 s->n_chan = board->n_aochan;
6238 s->maxdata = BIT(16) - 1;
6239 s->range_table = &range_unknown; /* XXX */
6240 s->insn_read = cs5529_ai_insn_read;
6241 s->insn_config = NULL;
6242 init_cs5529(dev);
6243 } else {
6244 s->type = COMEDI_SUBD_UNUSED;
6245 }
6246
6247 /* Serial */
6248 s = &dev->subdevices[NI_SERIAL_SUBDEV];
6249 s->type = COMEDI_SUBD_SERIAL;
6250 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6251 s->n_chan = 1;
6252 s->maxdata = 0xff;
6253 s->insn_config = ni_serial_insn_config;
6254 devpriv->serial_interval_ns = 0;
6255 devpriv->serial_hw_mode = 0;
6256
6257 /* RTSI */
6258 s = &dev->subdevices[NI_RTSI_SUBDEV];
6259 s->type = COMEDI_SUBD_DIO;
6260 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6261 s->n_chan = 8;
6262 s->maxdata = 1;
6263 s->insn_bits = ni_rtsi_insn_bits;
6264 s->insn_config = ni_rtsi_insn_config;
6265 ni_rtsi_init(dev);
6266
6267 /* allocate and initialize the gpct counter device */
6268 devpriv->counter_dev = ni_gpct_device_construct(dev,
6269 ni_gpct_write_register,
6270 ni_gpct_read_register,
6271 (devpriv->is_m_series)
6272 ? ni_gpct_variant_m_series
6273 : ni_gpct_variant_e_series,
6274 NUM_GPCT,
6275 NUM_GPCT,
6276 &devpriv->routing_tables);
6277 if (!devpriv->counter_dev)
6278 return -ENOMEM;
6279
6280 /* Counter (gpct) subdevices */
6281 for (i = 0; i < NUM_GPCT; ++i) {
6282 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
6283
6284 /* setup and initialize the counter */
6285 ni_tio_init_counter(gpct);
6286
6287 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
6288 s->type = COMEDI_SUBD_COUNTER;
6289 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
6290 s->n_chan = 3;
6291 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
6292 : 0x00ffffff;
6293 s->insn_read = ni_tio_insn_read;
6294 s->insn_write = ni_tio_insn_write;
6295 s->insn_config = ni_tio_insn_config;
6296 #ifdef PCIDMA
6297 if (dev->irq && devpriv->mite) {
6298 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
6299 s->len_chanlist = 1;
6300 s->do_cmdtest = ni_tio_cmdtest;
6301 s->do_cmd = ni_gpct_cmd;
6302 s->cancel = ni_gpct_cancel;
6303
6304 s->async_dma_dir = DMA_BIDIRECTIONAL;
6305 }
6306 #endif
6307 s->private = gpct;
6308 }
6309
6310 /* Initialize GPFO_{0,1} to produce output of counters */
6311 ni_set_gout_routing(0, 0, dev); /* output of counter 0; DAQ STC, p338 */
6312 ni_set_gout_routing(0, 1, dev); /* output of counter 1; DAQ STC, p338 */
6313
6314 /* Frequency output subdevice */
6315 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
6316 s->type = COMEDI_SUBD_COUNTER;
6317 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
6318 s->n_chan = 1;
6319 s->maxdata = 0xf;
6320 s->insn_read = ni_freq_out_insn_read;
6321 s->insn_write = ni_freq_out_insn_write;
6322 s->insn_config = ni_freq_out_insn_config;
6323
6324 if (dev->irq) {
6325 ni_stc_writew(dev,
6326 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
6327 (NISTC_INT_CTRL_3PIN_INT & 0) |
6328 NISTC_INT_CTRL_INTA_ENA |
6329 NISTC_INT_CTRL_INTB_ENA |
6330 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
6331 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
6332 NISTC_INT_CTRL_REG);
6333 }
6334
6335 /* DMA setup */
6336 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
6337 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
6338
6339 if (devpriv->is_6xxx) {
6340 ni_writeb(dev, 0, NI611X_MAGIC_REG);
6341 } else if (devpriv->is_m_series) {
6342 int channel;
6343
6344 for (channel = 0; channel < board->n_aochan; ++channel) {
6345 ni_writeb(dev, 0xf,
6346 NI_M_AO_WAVEFORM_ORDER_REG(channel));
6347 ni_writeb(dev, 0x0,
6348 NI_M_AO_REF_ATTENUATION_REG(channel));
6349 }
6350 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
6351 }
6352
6353 return 0;
6354 }
6355
mio_common_detach(struct comedi_device * dev)6356 static void mio_common_detach(struct comedi_device *dev)
6357 {
6358 struct ni_private *devpriv = dev->private;
6359
6360 if (devpriv)
6361 ni_gpct_device_destroy(devpriv->counter_dev);
6362 }
6363