Searched refs:MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 (Results 1 – 9 of 9) sorted by relevance
15 #define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 macro
16 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79
20 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
757 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */763 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
449 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000
336 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0 /* PSOC_SWD_IO */
324 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
755 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x110a0
589 fsl,pins = <MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0>;