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Searched refs:MP1_BASE__INST0_SEG5 (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_smu.c43 #define MP1_BASE__INST0_SEG5 0 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
Ddcn35_smu.c43 #define MP1_BASE__INST0_SEG5 0 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/
Dnavi10_ip_offset.h524 #define MP1_BASE__INST0_SEG5 0 macro
Dvega20_ip_offset.h549 #define MP1_BASE__INST0_SEG5 0 macro
Ddimgrey_cavefish_ip_offset.h709 #define MP1_BASE__INST0_SEG5 0 macro
Dbeige_goby_ip_offset.h836 #define MP1_BASE__INST0_SEG5 0 macro
Dvangogh_ip_offset.h959 #define MP1_BASE__INST0_SEG5 0 macro
Dyellow_carp_offset.h880 #define MP1_BASE__INST0_SEG5 0 macro
Darct_ip_offset.h697 #define MP1_BASE__INST0_SEG5 0x00F00000 macro
Daldebaran_ip_offset.h1008 #define MP1_BASE__INST0_SEG5 0 macro