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Searched refs:MP1_BASE__INST0_SEG4 (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_smu.c42 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
Ddcn35_smu.c42 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/
Dcyan_skillfish_ip_offset.h463 #define MP1_BASE__INST0_SEG4 0 macro
Dnavi10_ip_offset.h523 #define MP1_BASE__INST0_SEG4 0 macro
Dvega20_ip_offset.h548 #define MP1_BASE__INST0_SEG4 0 macro
Dnavi14_ip_offset.h701 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
Dnavi12_ip_offset.h701 #define MP1_BASE__INST0_SEG4 0x02400400 macro
Ddimgrey_cavefish_ip_offset.h708 #define MP1_BASE__INST0_SEG4 0x02400400 macro
Dsienna_cichlid_ip_offset.h708 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
Dbeige_goby_ip_offset.h835 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
Drenoir_ip_offset.h951 #define MP1_BASE__INST0_SEG4 0x00F00000 macro
Dvega10_ip_offset.h367 #define MP1_BASE__INST0_SEG4 0 macro
Dvangogh_ip_offset.h958 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
Dyellow_carp_offset.h879 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
Darct_ip_offset.h696 #define MP1_BASE__INST0_SEG4 0x00EC0000 macro
Daldebaran_ip_offset.h1007 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro