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Searched refs:MP1_BASE__INST0_SEG2 (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_smu.c40 #define MP1_BASE__INST0_SEG2 0x00DC0000 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
Ddcn35_smu.c40 #define MP1_BASE__INST0_SEG2 0x00DC0000 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/
Dcyan_skillfish_ip_offset.h461 #define MP1_BASE__INST0_SEG2 0 macro
Dnavi10_ip_offset.h521 #define MP1_BASE__INST0_SEG2 0 macro
Dvega20_ip_offset.h546 #define MP1_BASE__INST0_SEG2 0 macro
Dnavi14_ip_offset.h699 #define MP1_BASE__INST0_SEG2 0x00E00000 macro
Dnavi12_ip_offset.h699 #define MP1_BASE__INST0_SEG2 0x00EC0000 macro
Ddimgrey_cavefish_ip_offset.h706 #define MP1_BASE__INST0_SEG2 0x00EC0000 macro
Dsienna_cichlid_ip_offset.h706 #define MP1_BASE__INST0_SEG2 0x00E00000 macro
Dbeige_goby_ip_offset.h833 #define MP1_BASE__INST0_SEG2 0x00E00000 macro
Drenoir_ip_offset.h949 #define MP1_BASE__INST0_SEG2 0x00E80000 macro
Dvega10_ip_offset.h365 #define MP1_BASE__INST0_SEG2 0 macro
Dvangogh_ip_offset.h956 #define MP1_BASE__INST0_SEG2 0x00DC0000 macro
Dyellow_carp_offset.h877 #define MP1_BASE__INST0_SEG2 0x00DC0000 macro
Darct_ip_offset.h694 #define MP1_BASE__INST0_SEG2 0x00400400 macro
Daldebaran_ip_offset.h1005 #define MP1_BASE__INST0_SEG2 0x00E00000 macro