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Searched refs:MP1_BASE__INST0_SEG1 (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_smu.c39 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
Ddcn35_smu.c39 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/
Dcyan_skillfish_ip_offset.h460 #define MP1_BASE__INST0_SEG1 0 macro
Dnavi10_ip_offset.h520 #define MP1_BASE__INST0_SEG1 0 macro
Dvega20_ip_offset.h545 #define MP1_BASE__INST0_SEG1 0 macro
Dnavi14_ip_offset.h698 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
Dnavi12_ip_offset.h698 #define MP1_BASE__INST0_SEG1 0x00E80000 macro
Ddimgrey_cavefish_ip_offset.h705 #define MP1_BASE__INST0_SEG1 0x00E80000 macro
Dsienna_cichlid_ip_offset.h705 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
Dbeige_goby_ip_offset.h832 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
Drenoir_ip_offset.h948 #define MP1_BASE__INST0_SEG1 0x02400400 macro
Dvega10_ip_offset.h364 #define MP1_BASE__INST0_SEG1 0 macro
Dvangogh_ip_offset.h955 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
Dyellow_carp_offset.h876 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
Darct_ip_offset.h693 #define MP1_BASE__INST0_SEG1 0x00016200 macro
Daldebaran_ip_offset.h1004 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro