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Searched refs:MLX5_ST_SZ_DW (Results 1 – 25 of 92) sorted by relevance

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/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/
Dport.c89 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0}; in mlx5_query_pcam_reg()
101 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0}; in mlx5_query_mcam_reg()
113 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; in mlx5_query_qcam_reg()
150 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0}; in mlx5_query_port_ptys()
162 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0}; in mlx5_set_port_beacon()
163 u32 out[MLX5_ST_SZ_DW(mlcr_reg)]; in mlx5_set_port_beacon()
174 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_ib_port_oper()
204 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; in mlx5_set_port_admin_status()
205 u32 out[MLX5_ST_SZ_DW(paos_reg)]; in mlx5_set_port_admin_status()
218 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; in mlx5_query_port_admin_status()
[all …]
Dmr.c41 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {}; in mlx5_core_create_mkey()
62 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {}; in mlx5_core_destroy_mkey()
73 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {}; in mlx5_core_query_mkey()
95 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {}; in mlx5_core_create_psv()
96 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {}; in mlx5_core_create_psv()
119 u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {}; in mlx5_core_destroy_psv()
129 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in mlx5_core_get_terminate_scatter_list_mkey()
130 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in mlx5_core_get_terminate_scatter_list_mkey()
Dtransobj.c39 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {}; in mlx5_core_alloc_transport_domain()
40 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {}; in mlx5_core_alloc_transport_domain()
57 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {}; in mlx5_core_dealloc_transport_domain()
68 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {}; in mlx5_core_create_rq()
91 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {}; in mlx5_core_destroy_rq()
101 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {}; in mlx5_core_query_rq()
112 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {}; in mlx5_core_create_sq()
133 u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {}; in mlx5_core_destroy_sq()
142 u32 in[MLX5_ST_SZ_DW(query_sq_in)] = {}; in mlx5_core_query_sq()
177 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; in mlx5_core_create_tir()
[all …]
Dhwmon.c45 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_query_mtmp()
56 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_reset_max_temp()
57 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_reset_max_temp()
69 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_enable_max_temp()
70 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_enable_max_temp()
87 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_read()
168 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_init_channels_names()
249 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)]; in mlx5_hwmon_is_module_mon_cap()
269 u32 mtcap_out[MLX5_ST_SZ_DW(mtcap_reg)] = {}; in mlx5_hwmon_get_sensors_count()
270 u32 mtcap_in[MLX5_ST_SZ_DW(mtcap_reg)] = {}; in mlx5_hwmon_get_sensors_count()
[all …]
Dfw.c74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {}; in mlx5_query_board_id()
101 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {}; in mlx5_core_query_vendor_id()
289 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {}; in mlx5_cmd_init_hca()
309 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {}; in mlx5_cmd_teardown_hca()
317 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_force_teardown_hca()
318 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_force_teardown_hca()
346 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {}; in mlx5_cmd_fast_teardown_hca()
347 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {}; in mlx5_cmd_fast_teardown_hca()
408 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
409 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
[all …]
Dfs_cmd.c169 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {}; in mlx5_cmd_set_slave_root_fdb()
170 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {}; in mlx5_cmd_set_slave_root_fdb()
215 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {}; in mlx5_cmd_update_root_ft()
284 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {}; in mlx5_cmd_create_flow_table()
285 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {}; in mlx5_cmd_create_flow_table()
351 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {}; in mlx5_cmd_destroy_flow_table()
374 u32 in[MLX5_ST_SZ_DW(modify_flow_table_in)] = {}; in mlx5_cmd_modify_flow_table()
420 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {}; in mlx5_cmd_create_flow_group()
442 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {}; in mlx5_cmd_destroy_flow_group()
524 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {0}; in mlx5_cmd_set_fte()
[all …]
Decpf.c22 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {}; in mlx5_cmd_host_pf_enable_hca()
23 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; in mlx5_cmd_host_pf_enable_hca()
33 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {}; in mlx5_cmd_host_pf_disable_hca()
34 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; in mlx5_cmd_host_pf_disable_hca()
Dpd.c39 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; in mlx5_core_alloc_pd()
40 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; in mlx5_core_alloc_pd()
53 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in mlx5_core_dealloc_pd()
Dqos.c29 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_create_leaf_node()
47 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_create_inner_node()
75 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_update_node()
Dcq.c94 u32 din[MLX5_ST_SZ_DW(destroy_cq_in)] = {}; in mlx5_create_cq()
165 u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {}; in mlx5_core_destroy_cq()
191 u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {}; in mlx5_core_query_cq()
202 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {}; in mlx5_core_modify_cq()
215 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {}; in mlx5_core_modify_cq_moderation()
Dmcg.c40 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {}; in mlx5_core_attach_mcg()
53 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {}; in mlx5_core_detach_mcg()
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/sf/
Dcmd.c9 u32 out[MLX5_ST_SZ_DW(alloc_sf_out)] = {}; in mlx5_cmd_alloc_sf()
10 u32 in[MLX5_ST_SZ_DW(alloc_sf_in)] = {}; in mlx5_cmd_alloc_sf()
20 u32 out[MLX5_ST_SZ_DW(dealloc_sf_out)] = {}; in mlx5_cmd_dealloc_sf()
21 u32 in[MLX5_ST_SZ_DW(dealloc_sf_in)] = {}; in mlx5_cmd_dealloc_sf()
31 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {}; in mlx5_cmd_sf_enable_hca()
32 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; in mlx5_cmd_sf_enable_hca()
42 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {}; in mlx5_cmd_sf_disable_hca()
43 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; in mlx5_cmd_sf_disable_hca()
Dvhca_event.c35 u32 in[MLX5_ST_SZ_DW(query_vhca_state_in)] = {}; in mlx5_cmd_query_vhca_state()
47 u32 out[MLX5_ST_SZ_DW(modify_vhca_state_out)] = {}; in mlx5_cmd_modify_vhca_state()
58 u32 out[MLX5_ST_SZ_DW(modify_vhca_state_out)] = {}; in mlx5_modify_vhca_sw_id()
59 u32 in[MLX5_ST_SZ_DW(modify_vhca_state_in)] = {}; in mlx5_modify_vhca_sw_id()
72 u32 in[MLX5_ST_SZ_DW(modify_vhca_state_in)] = {}; in mlx5_vhca_event_arm()
83 u32 out[MLX5_ST_SZ_DW(query_vhca_state_out)] = {}; in mlx5_vhca_event_notify()
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dcmd.c40 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
75 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in mlx5_fpga_caps()
84 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_op()
85 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_op()
127 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_query()
128 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_query()
145 u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)] = {}; in mlx5_fpga_create_qp()
146 u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {}; in mlx5_fpga_create_qp()
167 u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {}; in mlx5_fpga_modify_qp()
181 u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)] = {}; in mlx5_fpga_query_qp()
[all …]
/linux-6.12.1/drivers/infiniband/hw/mlx5/
Dcmd.c10 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in mlx5r_cmd_query_special_mkeys()
11 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in mlx5r_cmd_query_special_mkeys()
48 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = {}; in mlx5_cmd_query_cong_params()
59 u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {}; in mlx5_cmd_destroy_tir()
69 u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {}; in mlx5_cmd_destroy_tis()
79 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {}; in mlx5_cmd_destroy_rqt()
90 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {}; in mlx5_cmd_alloc_transport_domain()
91 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {}; in mlx5_cmd_alloc_transport_domain()
109 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {}; in mlx5_cmd_dealloc_transport_domain()
120 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in mlx5_cmd_dealloc_pd()
[all …]
Dqpc.c198 u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {}; in _mlx5_core_destroy_dct()
235 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; in mlx5_qpc_create_qp()
268 u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {}; in mlx5_core_drain_dct()
309 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; in mlx5_core_destroy_qp()
325 u32 in[MLX5_ST_SZ_DW(set_delay_drop_params_in)] = {}; in mlx5_core_set_delay_drop()
531 u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {}; in mlx5_core_qp_query()
543 u32 in[MLX5_ST_SZ_DW(query_dct_in)] = {}; in mlx5_core_dct_query()
555 u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {}; in mlx5_core_xrcd_alloc()
556 u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {}; in mlx5_core_xrcd_alloc()
568 u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {}; in mlx5_core_xrcd_dealloc()
[all …]
Dsrq_cmd.c117 u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0}; in create_srq_cmd()
166 u32 in[MLX5_ST_SZ_DW(destroy_srq_in)] = {}; in destroy_srq_cmd()
178 u32 in[MLX5_ST_SZ_DW(arm_rq_in)] = {}; in arm_srq_cmd()
192 u32 in[MLX5_ST_SZ_DW(query_srq_in)] = {}; in query_srq_cmd()
220 u32 create_out[MLX5_ST_SZ_DW(create_xrc_srq_out)]; in create_xrc_srq_cmd()
273 u32 in[MLX5_ST_SZ_DW(destroy_xrc_srq_in)] = {}; in destroy_xrc_srq_cmd()
285 u32 in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {}; in arm_xrc_srq_cmd()
301 u32 in[MLX5_ST_SZ_DW(query_xrc_srq_in)] = {}; in query_xrc_srq_cmd()
388 u32 in[MLX5_ST_SZ_DW(destroy_rmp_in)] = {}; in destroy_rmp_cmd()
478 u32 create_out[MLX5_ST_SZ_DW(create_xrq_out)] = {0}; in create_xrq_cmd()
[all …]
/linux-6.12.1/drivers/vdpa/mlx5/core/
Dresources.c12 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; in alloc_pd()
13 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; in alloc_pd()
28 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in dealloc_pd()
39 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in get_null_mkey()
40 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in get_null_mkey()
53 u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {}; in create_uctx()
83 u32 out[MLX5_ST_SZ_DW(destroy_uctx_out)] = {}; in destroy_uctx()
84 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {}; in destroy_uctx()
97 u32 out[MLX5_ST_SZ_DW(create_tis_out)] = {}; in mlx5_vdpa_create_tis()
111 u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {}; in mlx5_vdpa_destroy_tis()
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_cmd.c12 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {}; in mlx5dr_cmd_query_esw_vport_context()
13 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {}; in mlx5dr_cmd_query_esw_vport_context()
38 u32 in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {}; in mlx5dr_cmd_query_gvmi()
93 u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {}; in dr_cmd_query_nic_vport_roce_en()
94 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {}; in dr_cmd_query_nic_vport_roce_en()
236 u32 out[MLX5_ST_SZ_DW(query_flow_table_out)] = {}; in mlx5dr_cmd_query_flow_table()
237 u32 in[MLX5_ST_SZ_DW(query_flow_table_in)] = {}; in mlx5dr_cmd_query_flow_table()
266 u32 out[MLX5_ST_SZ_DW(query_sampler_obj_out)] = {}; in mlx5dr_cmd_query_flow_sampler()
267 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5dr_cmd_query_flow_sampler()
293 u32 in[MLX5_ST_SZ_DW(sync_steering_in)] = {}; in mlx5dr_cmd_sync_steering()
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
Dmlx5hws_cmd.c37 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in hws_cmd_general_obj_destroy()
38 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in hws_cmd_general_obj_destroy()
51 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {0}; in mlx5hws_cmd_flow_table_create()
52 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {0}; in mlx5hws_cmd_flow_table_create()
78 u32 in[MLX5_ST_SZ_DW(modify_flow_table_in)] = {0}; in mlx5hws_cmd_flow_table_modify()
101 u32 out[MLX5_ST_SZ_DW(query_flow_table_out)] = {0}; in mlx5hws_cmd_flow_table_query()
102 u32 in[MLX5_ST_SZ_DW(query_flow_table_in)] = {0}; in mlx5hws_cmd_flow_table_query()
124 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {0}; in mlx5hws_cmd_flow_table_destroy()
143 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {0}; in hws_cmd_flow_group_create()
170 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {}; in hws_cmd_flow_group_destroy()
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/en/
Dport.c38 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_query_eth_autoneg()
55 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys()
56 u32 in[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys()
142 u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_query_sbpr()
154 u32 out[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_set_sbpr()
155 u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_set_sbpr()
171 u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_query_sbcm()
184 u32 out[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_set_sbcm()
185 u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_set_sbcm()
432 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_in_caps()
[all …]
Dtir.c12 MLX5_ST_SZ_DW(create_tir_in) > MLX5_ST_SZ_DW(modify_tir_in) ? \
13 MLX5_ST_SZ_DW(create_tir_in) : MLX5_ST_SZ_DW(modify_tir_in) \
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/diag/
Dfs_tracepoint.h109 __array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
110 __array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
111 __array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
193 __array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
194 __array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
195 __array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
196 __array(u32, value_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
197 __array(u32, value_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
198 __array(u32, value_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dgeneve.c22 u32 in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {}; in mlx5_geneve_tlv_option_create()
23 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_create()
53 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()
54 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()
Dclock.c146 u32 out[MLX5_ST_SZ_DW(mtutc_reg)] = {}; in mlx5_set_mtutc()
158 u32 out[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; in mlx5_is_ptm_source_time_available()
159 u32 in[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; in mlx5_is_ptm_source_time_available()
177 u32 out[MLX5_ST_SZ_DW(mtctr_reg)] = {0}; in mlx5_mtctr_syncdevicetime()
178 u32 in[MLX5_ST_SZ_DW(mtctr_reg)] = {0}; in mlx5_mtctr_syncdevicetime()
304 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; in mlx5_pps_out()
352 u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {}; in mlx5_ptp_settime_real_time()
427 u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {}; in mlx5_ptp_adjtime_real_time()
482 u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {}; in mlx5_ptp_freq_adj_real_time()
536 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; in mlx5_extts_configure()
[all …]

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