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Searched refs:MDIO_MMD_VEND2 (Results 1 – 25 of 29) sorted by relevance

12

/linux-6.12.1/drivers/net/pcs/
Dpcs-xpcs-nxp.c74 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL2, in nxp_sja1105_sgmii_pma_config()
89 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0, in nxp_sja1110_pma_config()
94 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1, in nxp_sja1110_pma_config()
100 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER1_0, in nxp_sja1110_pma_config()
107 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_0, val); in nxp_sja1110_pma_config()
113 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_1, val); in nxp_sja1110_pma_config()
122 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_TRIM, val); in nxp_sja1110_pma_config()
127 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DATAPATH_1, 0); in nxp_sja1110_pma_config()
134 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0, in nxp_sja1110_pma_config()
139 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL1, in nxp_sja1110_pma_config()
[all …]
Dpcs-xpcs.c272 dev = MDIO_MMD_VEND2; in xpcs_soft_reset()
375 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); in xpcs_config_usxgmii()
382 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); in xpcs_config_usxgmii()
628 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0); in xpcs_config_eee()
645 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret); in xpcs_config_eee()
649 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1); in xpcs_config_eee()
658 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret); in xpcs_config_eee()
686 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); in xpcs_config_aneg_c37_sgmii()
691 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, in xpcs_config_aneg_c37_sgmii()
697 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); in xpcs_config_aneg_c37_sgmii()
[all …]
Dpcs-xpcs-plat.c173 return xpcs_mmio_read_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg); in xpcs_mmio_read_c22()
175 return xpcs_mmio_read_reg_direct(pxpcs, MDIO_MMD_VEND2, reg); in xpcs_mmio_read_c22()
186 return xpcs_mmio_write_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg, val); in xpcs_mmio_write_c22()
188 return xpcs_mmio_write_reg_direct(pxpcs, MDIO_MMD_VEND2, reg, val); in xpcs_mmio_write_c22()
Dpcs-lynx.c45 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); in lynx_pcs_get_state_usxgmii()
54 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); in lynx_pcs_get_state_usxgmii()
164 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, in lynx_pcs_config_usxgmii()
/linux-6.12.1/drivers/net/ethernet/microchip/
Dlan743x_ethtool.c1244 { ETH_SR_MII_CTRL, MDIO_MMD_VEND2, 0x0000}, in lan743x_sgmii_regs()
1245 { ETH_SR_MII_STS, MDIO_MMD_VEND2, 0x0001}, in lan743x_sgmii_regs()
1246 { ETH_SR_MII_DEV_ID1, MDIO_MMD_VEND2, 0x0002}, in lan743x_sgmii_regs()
1247 { ETH_SR_MII_DEV_ID2, MDIO_MMD_VEND2, 0x0003}, in lan743x_sgmii_regs()
1248 { ETH_SR_MII_AN_ADV, MDIO_MMD_VEND2, 0x0004}, in lan743x_sgmii_regs()
1249 { ETH_SR_MII_LP_BABL, MDIO_MMD_VEND2, 0x0005}, in lan743x_sgmii_regs()
1250 { ETH_SR_MII_EXPN, MDIO_MMD_VEND2, 0x0006}, in lan743x_sgmii_regs()
1251 { ETH_SR_MII_EXT_STS, MDIO_MMD_VEND2, 0x000F}, in lan743x_sgmii_regs()
1252 { ETH_SR_MII_TIME_SYNC_ABL, MDIO_MMD_VEND2, 0x0708}, in lan743x_sgmii_regs()
1253 { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x0709}, in lan743x_sgmii_regs()
[all …]
Dlan743x_main.c1040 mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1056 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1061 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1066 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1099 mii_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR); in lan743x_serdes_clock_and_aneg_update()
1103 an_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, VR_MII_AN_CTRL); in lan743x_serdes_clock_and_aneg_update()
1107 dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1123 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1134 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, in lan743x_serdes_clock_and_aneg_update()
1139 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
[all …]
/linux-6.12.1/drivers/net/phy/
Ddp83td510.c185 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
191 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
197 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
202 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
217 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1); in dp83td510_handle_interrupt()
264 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_read_status()
307 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT); in dp83td510_get_sqi()
353 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, in dp83td510_cable_test_start()
379 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG1, in dp83td510_cable_test_start()
389 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2, in dp83td510_cable_test_start()
[all …]
Ddp83tg720.c92 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83tg720_cable_test_start()
97 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2, in dp83tg720_cable_test_start()
102 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3, in dp83tg720_cable_test_start()
107 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG4, in dp83tg720_cable_test_start()
112 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_0405, in dp83tg720_cable_test_start()
117 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_083F, in dp83tg720_cable_test_start()
123 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG, in dp83tg720_cable_test_start()
149 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG); in dp83tg720_cable_test_get_status()
162 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in dp83tg720_cable_test_get_status()
264 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_SQI_REG_1); in dp83tg720_get_sqi()
[all …]
Dmicrochip_t1s.c99 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb0_indirect_read()
104 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, in lan865x_revb0_indirect_read()
109 return phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_DATA); in lan865x_revb0_indirect_read()
138 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in lan865x_read_cfg_params()
153 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_write_cfg_params()
204 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb0_config_init()
223 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_revb1_config_init()
229 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_revb1_config_init()
245 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revb1_config_init()
Dintel-xway.c255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_config_init()
259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_config_init()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_config_init()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_config_init()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_config_init()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_config_init()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_config_init()
277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_config_init()
Dmarvell10g.c195 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); in mv3310_hwmon_read_temp_reg()
272 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
279 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, in mv3310_hwmon_config()
326 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_down()
335 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
349 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
667 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); in mv3310_get_mactype()
679 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
685 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
1338 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); in mv3110_get_wol()
[all …]
Dphy-c45.c1290 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1299 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1305 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1312 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1318 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); in genphy_c45_plca_get_cfg()
1351 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1366 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1383 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1391 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1406 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
[all …]
Dair_en8811h.c552 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_on_set()
579 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_blink_set()
709 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), in air_led_hw_control_set()
715 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), in air_led_hw_control_set()
737 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), in air_led_init()
752 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, in air_leds_init()
757 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, in air_leds_init()
764 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, in air_leds_init()
771 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, in air_leds_init()
Dmarvell-88x2222.c78 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
83 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
199 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
Dadin1100.c148 int rc = phy_read_mmd(phydev, MDIO_MMD_VEND2, in adin_phy_ack_intr()
168 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in adin_config_intr()
177 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2, in adin_phy_handle_interrupt()
Dmediatek-ge-soc.c364 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, in rext_fill_result()
1148 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_hw_led_on_set()
1171 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_hw_led_blink_set()
1247 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mt798x_phy_led_hw_control_get()
1253 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mt798x_phy_led_hw_control_get()
1353 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_led_hw_control_set()
1364 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_led_hw_control_set()
1392 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mt7988_phy_fix_leds_polarities()
Dmxl-gpy.c704 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
711 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
718 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
731 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
747 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
Drealtek.c978 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR, in rtl822x_c45_config_aneg()
998 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, in rtl822x_c45_read_status()
1010 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR); in rtl822x_c45_read_status()
Dnxp-c45-tja11xx-macsec.c301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); in nxp_c45_macsec_write()
307 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); in nxp_c45_macsec_write()
321 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); in nxp_c45_macsec_read()
327 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); in nxp_c45_macsec_read()
/linux-6.12.1/drivers/net/dsa/sja1105/
Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read_c45()
23 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1105_pcs_mdio_read_c45()
25 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1105_pcs_mdio_read_c45()
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write_c45()
67 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1110_pcs_mdio_read_c45()
69 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1110_pcs_mdio_read_c45()
/linux-6.12.1/drivers/net/ethernet/amd/xgbe/
Dxgbe-mdio.c151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_clear_interrupts()
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_clear_interrupts()
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_disable_interrupts()
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_disable_interrupts()
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_enable_interrupts()
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_enable_interrupts()
368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
663 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_isr()
670 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_isr()
[all …]
/linux-6.12.1/include/uapi/linux/
Dmdio.h29 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ macro
160 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
/linux-6.12.1/rust/kernel/net/phy/
Dreg.rs173 pub const VEND2: Self = Mmd(uapi::MDIO_MMD_VEND2 as u8);
/linux-6.12.1/drivers/net/dsa/
Dmt7530.c101 MII_MMD_CTRL, MDIO_MMD_VEND2); in core_write()
113 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); in core_write()
138 MII_MMD_CTRL, MDIO_MMD_VEND2); in core_rmw()
150 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); in core_rmw()
2670 MDIO_MMD_VEND2, CORE_PLL_GROUP4); in mt7531_setup()
2675 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); in mt7531_setup()

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