Searched refs:MAX_MPCC (Results 1 – 14 of 14) sorted by relevance
191 uint32_t MPCC_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \192 uint32_t MPCC_GAMUT_REMAP_MODE[MAX_MPCC]; \193 uint32_t MPC_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \194 uint32_t MPC_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \195 uint32_t MPC_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \196 uint32_t MPC_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \231 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \232 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \233 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \234 uint32_t MPCC_OGAM_RAMA_OFFSET_B[MAX_MPCC]; \[all …]
1555 for (i = 0; i < MAX_MPCC; i++) in dcn30_mpc_construct()
37 uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \38 uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_MODE[MAX_MPCC]; \39 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \40 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \41 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \42 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \43 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \44 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \45 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \46 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \[all …]
651 for (i = 0; i < MAX_MPCC; i++) in dcn401_mpc_construct()
89 uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \90 uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \91 uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \92 uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \93 uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \94 uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \95 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \96 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \97 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \98 uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \[all …]
607 for (i = 0; i < MAX_MPCC; i++) in dcn20_mpc_construct()
50 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \51 uint32_t MPCC_BOT_SEL[MAX_MPCC]; \52 uint32_t MPCC_CONTROL[MAX_MPCC]; \53 uint32_t MPCC_STATUS[MAX_MPCC]; \54 uint32_t MPCC_OPP_ID[MAX_MPCC]; \55 uint32_t MPCC_BG_G_Y[MAX_MPCC]; \56 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \57 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \58 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \60 uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \
534 for (i = 0; i < MAX_MPCC; i++) in dcn10_mpc_construct()
58 #define MAX_MPCC 6 macro282 struct mpcc mpcc_array[MAX_MPCC];
123 for (i = 0; i < MAX_MPCC; i++) in dcn201_mpc_construct()
1048 for (i = 0; i < MAX_MPCC; i++) in dcn32_mpc_construct()
832 if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id])) in dcn35_init_pipes()
3483 if (s.dpp_id < MAX_MPCC) in acquire_resource_from_hw_enabled_state()3487 if (s.bot_mpcc_id < MAX_MPCC) in acquire_resource_from_hw_enabled_state()
1492 if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id])) in dcn10_init_pipes()