Searched refs:KVM_REG_RISCV_CSR (Results 1 – 4 of 4) sorted by relevance
116 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): in filter_reg()117 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1): in filter_reg()118 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2): in filter_reg()119 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh): in filter_reg()120 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph): in filter_reg()121 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h): in filter_reg()122 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h): in filter_reg()327 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); in csr_id_to_str()330 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR); in csr_id_to_str()637 case KVM_REG_RISCV_CSR: in print_reg()[all …]
501 KVM_REG_RISCV_CSR); in kvm_riscv_vcpu_get_reg_csr()543 KVM_REG_RISCV_CSR); in kvm_riscv_vcpu_set_reg_csr()839 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()856 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()874 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()1215 case KVM_REG_RISCV_CSR: in kvm_riscv_vcpu_set_reg()1248 case KVM_REG_RISCV_CSR: in kvm_riscv_vcpu_get_reg()
34 #define RISCV_GENERAL_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
230 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) macro