Searched refs:JZ4780_CLK_MPLL (Results 1 – 3 of 3) sorted by relevance
| /linux-6.12.1/drivers/clk/ingenic/ |
| D | jz4780-cgu.c | 298 [JZ4780_CLK_MPLL] = {
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
366 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
374 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
398 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
405 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
427 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
435 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
443 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
470 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
[all …]
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | ingenic,jz4780-cgu.h | 18 #define JZ4780_CLK_MPLL 3 macro
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| /linux-6.12.1/arch/mips/boot/dts/ingenic/ |
| D | ci20.dts | 173 <&cgu JZ4780_CLK_MPLL>,
175 <0>, <&cgu JZ4780_CLK_MPLL>;
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