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Searched refs:JH7110_SYSCLK_DDR_AXI (Results 1 – 2 of 2) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dstarfive,jh7110-crg.h61 #define JH7110_SYSCLK_DDR_AXI 44 macro
/linux-6.12.1/drivers/clk/starfive/
Dclk-starfive-jh7110-sys.c104 JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),