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Searched refs:JH7110_STGCLK_PCIE0_AXI_MST0 (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dstarfive,jh7110-crg.h237 #define JH7110_STGCLK_PCIE0_AXI_MST0 8 macro
/linux-6.12.1/drivers/clk/starfive/
Dclk-starfive-jh7110-stg.c41 JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1247 <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,