Searched refs:JH7110_STGCLK_PCIE0_AXI_MST0 (Results 1 – 3 of 3) sorted by relevance
237 #define JH7110_STGCLK_PCIE0_AXI_MST0 8 macro
41 JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
1247 <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,