Searched refs:IOMEM (Results 1 – 25 of 40) sorted by relevance
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19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)47 #define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000)52 #define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)55 #define VA_SYSRAM0_BASE IOMEM(0xF9800000)59 #define VA_PERIP_GRP1_BASE IOMEM(0xFD000000)61 #define VA_UART_BASE IOMEM(0xFD000000)64 #define VA_MISC_BASE IOMEM(0xFD700000)67 #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000)[all …]
39 static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
24 #define PERIPH_VIRT IOMEM(0xf2000000)32 #define SMEMC_VIRT IOMEM(0xf6000000)39 #define DMEMC_VIRT IOMEM(0xf6100000)51 #define NAND_VIRT IOMEM(0xf6300000)58 #define IMEMC_VIRT IOMEM(0xfe000000)
32 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
13 #define SMEMC_VIRT IOMEM(0xf6000000)
34 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */37 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */40 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */43 #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)46 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)49 #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
16 #define APB_VIRT_BASE IOMEM(0xfe000000)20 #define AXI_VIRT_BASE IOMEM(0xfe200000)24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
98 #define IO_IRAM_VIRT IOMEM(0xFE400000)102 #define IO_CPU_VIRT IOMEM(0xFE440000)106 #define IO_PPSB_VIRT IOMEM(0xFE200000)110 #define IO_APB_VIRT IOMEM(0xFE000000)
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)40 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000)44 #define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000)
14 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) macro15 #define RT2880_SYSC_BASE IOMEM(0x00300000)
10 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) macro15 #define MT7621_SYSC_BASE IOMEM(0x1E000000)
14 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) macro15 #define MT7620_SYSC_BASE IOMEM(0x10000000)
46 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) macro47 #define RT305X_SYSC_BASE IOMEM(0x10000000)
13 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) macro16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
36 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )40 #define __MREG(x) IOMEM(io_p2v(x))
12 #define IOMEM(x) (x) macro
30 #define EASI_BASE IOMEM(0xe5000000)34 #define IO_BASE IOMEM(0xe0000000)
5 #define V7M_SCS_ICTR IOMEM(0xe000e004)8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
29 #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
66 return readl(IOMEM(c->regs + section_offset + port_offset)); in zevio_gpio_port_get()73 writel(val, IOMEM(c->regs + section_offset + port_offset)); in zevio_gpio_port_set()
92 #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
19 #define CLPS711X_VIRT_BASE IOMEM(0xfeff4000)
54 omap_sram_ceil = IOMEM(new_ceil); in omap_sram_push_address()