Searched refs:INTEN0 (Results 1 – 2 of 2) sorted by relevance
382 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()396 writel(VAL0 | STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()403 writel(STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()410 writel(VAL0 | STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()447 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); in amd8111e_restart()449 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); in amd8111e_restart()544 writel(INTEN0_CLEAR, mmio + INTEN0); in amd8111e_init_hw_default()783 writel(VAL0|RINTEN0, mmio + INTEN0); in amd8111e_rx_poll()1096 intren0 = readl(mmio + INTEN0); in amd8111e_interrupt()1112 writel(RINTEN0, mmio + INTEN0); in amd8111e_interrupt()[all …]
45 #define INTEN0 0x40 /* Interrupt0 enable register*/ macro