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Searched refs:INTEL_ARCH_EVENT_MASK (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/arch/x86/events/
Dperf_event.h99 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && in is_metric_event()
100 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); in is_metric_event()
105 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; in is_slots_event()
443 INTEL_ARCH_EVENT_MASK)
449 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
457 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
460 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
464 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
468 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
472 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
[all …]
/linux-6.12.1/arch/x86/include/asm/
Dperf_event.h63 #define INTEL_ARCH_EVENT_MASK \ macro
/linux-6.12.1/arch/x86/events/intel/
Dcore.c3261 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; in intel_fixup_er()
3265 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; in intel_fixup_er()
3922 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); in is_mem_loads_event()
3927 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); in is_mem_loads_aux_event()
3960 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) in intel_pmu_hw_config()
3987 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) in intel_pmu_hw_config()
4598 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == in erratum_hsw11()
Dds.c1324 ((attr->config & INTEL_ARCH_EVENT_MASK) == in pebs_update_adaptive_cfg()