Searched refs:IMX93_CLK_SYS_PLL_PFD1_DIV2 (Results 1 – 5 of 5) sorted by relevance
57 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,58 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,59 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
453 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;861 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;1125 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,1127 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;1151 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,1293 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;1315 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
528 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
15 #define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 macro
286 clks[IMX93_CLK_SYS_PLL_PFD1_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd1_div2", in imx93_clocks_probe()