Searched refs:IMX93_CLK_SYS_PLL_PFD0_DIV2 (Results 1 – 4 of 4) sorted by relevance
13 #define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 macro
107 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
1126 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,1152 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
283 clks[IMX93_CLK_SYS_PLL_PFD0_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd0_div2", in imx93_clocks_probe()