Searched refs:IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE (Results 1 – 2 of 2) sorted by relevance
45 #define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 macro
180 …clks[IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE] = imx_clk_hw_gate_dis("spll3_pfd0_div2_gate", "spll3_pfd0",… in imx8ulp_clk_cgc1_init()