Searched refs:IMX7ULP_CLK_NIC1_BUS_DIV (Results 1 – 3 of 3) sorted by relevance
132 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,223 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,237 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,271 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,303 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,333 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;346 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
50 #define IMX7ULP_CLK_NIC1_BUS_DIV 37 macro
120 …hws[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_hw_divider_flags("nic1_bus_clk", "nic0_clk", base + 0x40, … in imx7ulp_clk_scg1_init()