Searched refs:IMX6SX_CLK_PLL4_AUDIO_DIV (Results 1 – 3 of 3) sorted by relevance
250 hws[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", in imx6sx_clocks_init()528 clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000); in imx6sx_clocks_init()530 clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()536 clk_set_parent(hws[IMX6SX_CLK_SSI1_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()537 clk_set_parent(hws[IMX6SX_CLK_SSI2_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()538 clk_set_parent(hws[IMX6SX_CLK_SSI3_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()543 clk_set_parent(hws[IMX6SX_CLK_ESAI_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); in imx6sx_clocks_init()
41 #define IMX6SX_CLK_PLL4_AUDIO_DIV 32 macro
131 assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;