Searched refs:IMX6QDL_CLK_PLL4_POST_DIV (Results 1 – 3 of 3) sorted by relevance
203 #define IMX6QDL_CLK_PLL4_POST_DIV 193 macro
266 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
598 …hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio"… in imx6q_clocks_init()