Searched refs:IMX6QDL_CLK_IPU2_DI0_PRE_SEL (Results 1 – 4 of 4) sorted by relevance
64 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
402 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
46 #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 macro
665 …hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, i… in imx6q_clocks_init()934 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()