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Searched refs:HHI_VID_PLL_CLK_DIV (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/meson/
Dmeson_vclk.c50 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
141 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
204 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
208 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
215 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
219 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
221 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
[all …]
/linux-6.12.1/drivers/clk/meson/
Daxg.h69 #define HHI_VID_PLL_CLK_DIV 0x1a0 macro
Dgxbb.h52 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
Dg12a.h69 #define HHI_VID_PLL_CLK_DIV 0x1A0 macro
Dgxbb.c1780 .reg_off = HHI_VID_PLL_CLK_DIV,
1785 .reg_off = HHI_VID_PLL_CLK_DIV,
1823 .offset = HHI_VID_PLL_CLK_DIV,
1842 .offset = HHI_VID_PLL_CLK_DIV,
Dg12a.c2643 .reg_off = HHI_VID_PLL_CLK_DIV,
2648 .reg_off = HHI_VID_PLL_CLK_DIV,
2669 .offset = HHI_VID_PLL_CLK_DIV,
2688 .offset = HHI_VID_PLL_CLK_DIV,