Searched refs:HDMI_TXPHY_PAD_CFG_CTRL (Results 1 – 6 of 6) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/omapdrm/dss/ |
D | hdmi_phy.c | 27 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_phy_dump() 119 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes() 120 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes()
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D | hdmi5.c | 91 v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler() 94 hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); in hdmi_irq_handler() 101 REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
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D | hdmi.h | 77 #define HDMI_TXPHY_PAD_CFG_CTRL 0xC macro
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/linux-6.12.1/drivers/video/fbdev/omap2/omapfb/dss/ |
D | hdmi_phy.c | 36 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_phy_dump() 128 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes() 129 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes()
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D | hdmi5.c | 88 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler() 91 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); in hdmi_irq_handler() 98 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
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D | hdmi.h | 73 #define HDMI_TXPHY_PAD_CFG_CTRL 0xC macro
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