Searched refs:HDMI_ACR_CTS_48 (Results 1 – 16 of 16) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_stream_encoder.h | 186 SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ 264 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ 458 uint8_t HDMI_ACR_CTS_48; member 590 uint32_t HDMI_ACR_CTS_48; member
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D | dce_stream_encoder.c | 1312 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in dce110_se_setup_hdmi_audio()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
D | dcn32_dio_stream_encoder.h | 81 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
D | dcn401_dio_stream_encoder.h | 83 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
D | dcn10_stream_encoder.h | 256 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ 472 type HDMI_ACR_CTS_48;\
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D | dcn10_stream_encoder.c | 1298 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in enc1_se_setup_hdmi_audio()
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/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | evergreen_hdmi.c | 95 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
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D | rv770d.h | 796 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) macro
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D | evergreend.h | 650 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) macro
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
D | dcn35_dio_stream_encoder.h | 161 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
D | dcn30_dio_stream_encoder.h | 160 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
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D | dcn30_dio_stream_encoder.c | 803 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in enc3_se_setup_hdmi_audio()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
D | dcn314_dio_stream_encoder.h | 160 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | dce_v6_0.c | 1457 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v6_0_audio_set_acr()
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D | dce_v10_0.c | 1506 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v10_0_afmt_update_ACR()
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D | dce_v11_0.c | 1555 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v11_0_afmt_update_ACR()
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