Searched refs:HDMI_ACR_48_1 (Results 1 – 17 of 17) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_stream_encoder.h | 82 SRI(HDMI_ACR_48_1, DIG, id),\
187 SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
683 uint32_t HDMI_ACR_48_1; member
|
| D | dce_stream_encoder.c | 1315 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); in dce110_se_setup_hdmi_audio()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| D | dcn10_stream_encoder.h | 73 SRI(HDMI_ACR_48_1, DIG, id),\
166 uint32_t HDMI_ACR_48_1; member
|
| D | dcn10_stream_encoder.c | 1301 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); in enc1_se_setup_hdmi_audio()
|
| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | evergreen_hdmi.c | 96 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); in evergreen_hdmi_update_acr()
|
| D | rv770d.h | 797 #define HDMI_ACR_48_1 0x74c0 macro
|
| D | evergreend.h | 651 #define HDMI_ACR_48_1 0x70f0 macro
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| D | dcn35_resource.h | 106 SRI_ARR(HDMI_ACR_48_1, DIG, id),\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| D | dcn35_dio_stream_encoder.h | 74 SRI(HDMI_ACR_48_1, DIG, id),\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| D | dcn30_dio_stream_encoder.h | 75 SRI(HDMI_ACR_48_1, DIG, id),\
|
| D | dcn30_dio_stream_encoder.c | 806 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); in enc3_se_setup_hdmi_audio()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| D | dcn314_dio_stream_encoder.h | 76 SRI(HDMI_ACR_48_1, DIG, id),\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| D | dcn401_resource.h | 197 SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource.h | 282 SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \
|
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v6_0.c | 1460 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v6_0_audio_set_acr()
|
| D | dce_v10_0.c | 1509 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v10_0_afmt_update_ACR()
|
| D | dce_v11_0.c | 1558 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v11_0_afmt_update_ACR()
|