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Searched refs:HDMI_ACR_44_1 (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h80 SRI(HDMI_ACR_44_1, DIG, id),\
185 SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
681 uint32_t HDMI_ACR_44_1; member
Ddce_stream_encoder.c1309 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in dce110_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/
Ddcn10_stream_encoder.h71 SRI(HDMI_ACR_44_1, DIG, id),\
164 uint32_t HDMI_ACR_44_1; member
Ddcn10_stream_encoder.c1295 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in enc1_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/radeon/
Devergreen_hdmi.c93 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
Drv770d.h793 #define HDMI_ACR_44_1 0x74b8 macro
Devergreend.h647 #define HDMI_ACR_44_1 0x70e8 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/
Ddcn35_resource.h104 SRI_ARR(HDMI_ACR_44_1, DIG, id),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn35/
Ddcn35_dio_stream_encoder.h72 SRI(HDMI_ACR_44_1, DIG, id),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/
Ddcn30_dio_stream_encoder.h73 SRI(HDMI_ACR_44_1, DIG, id),\
Ddcn30_dio_stream_encoder.c800 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in enc3_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn314/
Ddcn314_dio_stream_encoder.h74 SRI(HDMI_ACR_44_1, DIG, id),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.h196 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource.h281 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1453 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v6_0_audio_set_acr()
Ddce_v10_0.c1502 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v10_0_afmt_update_ACR()
Ddce_v11_0.c1551 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v11_0_afmt_update_ACR()