Searched refs:HDMI_ACR_44_0 (Results 1 – 17 of 17) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_stream_encoder.h | 79 SRI(HDMI_ACR_44_0, DIG, id),\
184 SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
680 uint32_t HDMI_ACR_44_0; member
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| D | dce_stream_encoder.c | 1306 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); in dce110_se_setup_hdmi_audio()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| D | dcn10_stream_encoder.h | 70 SRI(HDMI_ACR_44_0, DIG, id),\
163 uint32_t HDMI_ACR_44_0; member
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| D | dcn10_stream_encoder.c | 1292 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); in enc1_se_setup_hdmi_audio()
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | evergreen_hdmi.c | 92 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
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| D | rv770d.h | 791 #define HDMI_ACR_44_0 0x74b4 macro
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| D | evergreend.h | 645 #define HDMI_ACR_44_0 0x70e4 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| D | dcn35_resource.h | 103 SRI_ARR(HDMI_ACR_44_0, DIG, id),\
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| D | dcn35_dio_stream_encoder.h | 71 SRI(HDMI_ACR_44_0, DIG, id),\
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| D | dcn30_dio_stream_encoder.h | 72 SRI(HDMI_ACR_44_0, DIG, id),\
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| D | dcn30_dio_stream_encoder.c | 797 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); in enc3_se_setup_hdmi_audio()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| D | dcn314_dio_stream_encoder.h | 73 SRI(HDMI_ACR_44_0, DIG, id),\
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| D | dcn401_resource.h | 196 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource.h | 281 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v6_0.c | 1450 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v6_0_audio_set_acr()
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| D | dce_v10_0.c | 1499 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v10_0_afmt_update_ACR()
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| D | dce_v11_0.c | 1548 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v11_0_afmt_update_ACR()
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