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Searched refs:HDA_DSP_BAR (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/sound/soc/sof/intel/
Dmtl.c27 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
28 {"fw_regs", HDA_DSP_BAR, MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},
37 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR, in mtl_ipc_host_done()
42 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA, in mtl_ipc_host_done()
52 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA, in mtl_ipc_dsp_done()
56 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, in mtl_ipc_dsp_done()
70 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; in mtl_dsp_check_ipc_irq()
71 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); in mtl_dsp_check_ipc_irq()
89 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; in mtl_dsp_check_sdw_irq()
90 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); in mtl_dsp_check_sdw_irq()
[all …]
Dcnl.c30 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
44 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); in cnl_ipc4_irq_thread()
45 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); in cnl_ipc4_irq_thread()
48 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, in cnl_ipc4_irq_thread()
59 u32 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, in cnl_ipc4_irq_thread()
126 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); in cnl_ipc_irq_thread()
127 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); in cnl_ipc_irq_thread()
128 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD); in cnl_ipc_irq_thread()
129 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR); in cnl_ipc_irq_thread()
139 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, in cnl_ipc_irq_thread()
[all …]
Dhda-ipc.c35 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, in hda_dsp_ipc_host_done()
41 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, in hda_dsp_ipc_host_done()
53 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, in hda_dsp_ipc_dsp_done()
59 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, in hda_dsp_ipc_dsp_done()
70 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI, in hda_dsp_ipc_send_msg()
121 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE, msg_data->extension); in hda_dsp_ipc4_send_msg()
122 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI, in hda_dsp_ipc4_send_msg()
175 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); in hda_dsp_ipc4_irq_thread()
176 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); in hda_dsp_ipc4_irq_thread()
180 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL, in hda_dsp_ipc4_irq_thread()
[all …]
Dhda-loader-skl.c142 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, in cl_skl_cldma_stream_run()
151 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, in cl_skl_cldma_stream_run()
175 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, in cl_skl_cldma_stream_clear()
178 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, in cl_skl_cldma_stream_clear()
182 snd_sof_dsp_write(sdev, HDA_DSP_BAR, in cl_skl_cldma_stream_clear()
184 snd_sof_dsp_write(sdev, HDA_DSP_BAR, in cl_skl_cldma_stream_clear()
188 snd_sof_dsp_write(sdev, HDA_DSP_BAR, in cl_skl_cldma_stream_clear()
191 snd_sof_dsp_write(sdev, HDA_DSP_BAR, in cl_skl_cldma_stream_clear()
201 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, in cl_skl_cldma_setup_spb()
206 snd_sof_dsp_write(sdev, HDA_DSP_BAR, in cl_skl_cldma_setup_spb()
[all …]
Dhda-dsp.c137 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, in hda_dsp_core_reset_enter()
142 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, in hda_dsp_core_reset_enter()
155 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, in hda_dsp_core_reset_enter()
175 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, in hda_dsp_core_reset_leave()
182 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, in hda_dsp_core_reset_leave()
196 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, in hda_dsp_core_reset_leave()
211 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, in hda_dsp_core_stall_reset()
226 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS); in hda_dsp_core_is_enabled()
258 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, in hda_dsp_core_run()
294 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, in hda_dsp_core_power_up()
[all …]
Dtgl.c22 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
28 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
29 {"fw_regs", HDA_DSP_BAR, SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},
Dhda-loader.c37 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, in hda_ssp_set_cbp_cfp()
130 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); in cl_dsp_init()
143 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, in cl_dsp_init()
159 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, in cl_dsp_init()
187 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, in cl_dsp_init()
310 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, in hda_cl_copy_fw()
Dhda.c165 res.mmio_base = sdev->bar[HDA_DSP_BAR]; in hda_sdw_probe()
270 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); in hda_common_check_sdw_irq()
311 snd_sof_dsp_read(sdev, HDA_DSP_BAR, in hda_sdw_check_wakeen_irq_common()
776 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); in hda_dsp_probe()
777 if (!sdev->bar[HDA_DSP_BAR]) { in hda_dsp_probe()
783 sdev->mmio_bar = HDA_DSP_BAR; in hda_dsp_probe()
784 sdev->mailbox_bar = HDA_DSP_BAR; in hda_dsp_probe()
893 iounmap(sdev->bar[HDA_DSP_BAR]); in hda_dsp_probe()
951 iounmap(sdev->bar[HDA_DSP_BAR]); in hda_dsp_remove()
Dicl.c27 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
43 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, in icl_dsp_core_stall()
Dlnl.c30 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
31 {"fw_regs", HDA_DSP_BAR, MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},
Dskl.c38 {"dsp", HDA_DSP_BAR, 0, 0x10000},
Dapl.c27 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
Dhda.h160 #define HDA_DSP_BAR 4 macro