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Searched refs:HCLK_I2S0_8CH (Results 1 – 19 of 19) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Drk3228-cru.h120 #define HCLK_I2S0_8CH 442 macro
Drk3308-cru.h158 #define HCLK_I2S0_8CH 164 macro
Drv1108-cru.h139 #define HCLK_I2S0_8CH 320 macro
Drk3328-cru.h173 #define HCLK_I2S0_8CH 311 macro
Drk3399-cru.h308 #define HCLK_I2S0_8CH 468 macro
Drockchip,rk3588-cru.h55 #define HCLK_I2S0_8CH 40 macro
Drk3568-cru.h121 #define HCLK_I2S0_8CH 57 macro
/linux-6.12.1/drivers/clk/rockchip/
Dclk-rk3228.c587 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
Dclk-rv1108.c562 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0,
Dclk-rk3328.c758 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS),
Dclk-rk3308.c836 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 4, GFLAGS),
Dclk-rk3399.c1022 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
Dclk-rk3568.c617 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0,
Dclk-rk3588.c931 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0,
/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drk322x.dtsi157 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3328.dtsi246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
Drk356x.dtsi1131 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
Drk3399-base.dtsi1784 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
Drk3588-base.dtsi1886 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;