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Searched refs:GUC_MCR_REG_ADD (Results 1 – 1 of 1) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_ads.c369 #define GUC_MCR_REG_ADD(gt, regset, reg, masked) \ macro
405 ret |= GUC_MCR_REG_ADD(gt, regset, wa->mcr_reg, wa->masked_reg); in guc_mmio_regset_init()
416 ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false); in guc_mmio_regset_init()
421 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false); in guc_mmio_regset_init()
422 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false); in guc_mmio_regset_init()
423 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false); in guc_mmio_regset_init()
424 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false); in guc_mmio_regset_init()
425 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false); in guc_mmio_regset_init()
426 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false); in guc_mmio_regset_init()
427 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false); in guc_mmio_regset_init()