Searched refs:GPCR (Results 1 – 9 of 9) sorted by relevance
126 GPCR = SDA; in adv7171_start()142 GPCR = SCK; in adv7171_send()147 GPCR = SDA; in adv7171_send()152 GPCR = SCK; in adv7171_send()162 GPCR = SCK | SDA; in adv7171_send()176 GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ in adv7171_write()191 GPCR = (~gplr) & (SDA | SCK | MOD); in adv7171_write()531 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; in assabet_init()539 GPCR = GPIO_GPIO27; in assabet_init()
109 GPCR = ~gpio; in sa11x0_pm_enter()
421 GPCR = GPIO_MBGNT; in sa1110_mb_disable()440 GPCR = GPIO_MBGNT; in sa1110_mb_enable()
115 GPCR = GPIO_GPIO25; in jornada_ssp_start()
269 GPCR = GPIO_GPIO20; /* stop gpio20 */ in jornada720_init()
285 GPCR = 0x0fffffff; /* All outputs are set low by default */ in h3xxx_map_io()
36 #define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24) macro372 GPCR(i * 32) = ~PGSR(i); in pxa2xx_mfp_suspend()396 GPCR(i * 32) = ~saved_gplr[i]; in pxa2xx_mfp_resume()
36 #define GPCR 0x04c /* Pin clear w/o */ macro99 reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift); in tng_gpio_set()
1108 #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ macro