Searched refs:GEN8_L3SQCREG4 (Results 1 – 6 of 6) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/i915/gt/ |
| D | intel_workarounds.c | 1900 whitelist_mcr_reg(w, GEN8_L3SQCREG4); in skl_whitelist_build()
1921 whitelist_mcr_reg(w, GEN8_L3SQCREG4); in kbl_whitelist_build()
2334 GEN8_L3SQCREG4, in rcs_engine_wa_init()
2463 GEN8_L3SQCREG4, in rcs_engine_wa_init()
2469 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, in rcs_engine_wa_init()
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| D | intel_lrc.c | 1639 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1645 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1654 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
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| D | intel_gt_regs.h | 991 #define GEN8_L3SQCREG4 MCR_REG(0xb118) macro
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | intel_gvt_mmio_table.c | 837 MMIO_D(GEN8_L3SQCREG4); in iterate_bdw_plus_mmio()
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| /linux-6.12.1/drivers/gpu/drm/i915/gvt/ |
| D | cmd_parser.c | 925 if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) || in cmd_reg_handler()
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| D | handlers.c | 2554 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
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