/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | gfx_v10_0.c | 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), [all …]
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D | imu_v11_0.c | 101 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v11_0_load_microcode() 104 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v11_0_load_microcode() 106 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode() 113 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v11_0_load_microcode() 116 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v11_0_load_microcode() 118 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode() 128 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v11_0_wait_for_reset_status() 147 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); in imu_v11_0_setup() 148 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); in imu_v11_0_setup() 151 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); in imu_v11_0_setup() [all …]
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D | imu_v11_0_3.c | 31 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000), 32 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000), 33 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000), 34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000), 35 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000), 36 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000), 37 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000), 38 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000), 39 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000), 40 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000), [all …]
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D | imu_v12_0.c | 96 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v12_0_load_microcode() 99 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode() 101 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode() 108 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v12_0_load_microcode() 111 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode() 113 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode() 124 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v12_0_wait_for_reset_status() 142 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); in imu_v12_0_setup() 143 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); in imu_v12_0_setup() 146 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); in imu_v12_0_setup() [all …]
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D | gfx_v9_4.c | 42 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 }, 43 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 }, 45 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 }, 46 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 }, 47 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 }, 49 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 }, 50 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 }, 52 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 }, 53 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1 }, 54 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1 }, [all …]
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D | gfxhub_v1_2.c | 39 return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24; in gfxhub_v1_2_get_mc_fb_offset() 52 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_setup_vm_pt_regs() 57 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_setup_vm_pt_regs() 92 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 95 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 99 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 102 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 106 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 109 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 113 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() [all …]
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D | gfx_v9_4_2.c | 64 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920), 65 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9e88b), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x2bc3369b), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0xfb74ee), [all …]
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D | gfxhub_v2_1.c | 110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location() 120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset() 128 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_1_setup_vm_pt_regs() 132 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_1_setup_vm_pt_regs() 143 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs() 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_1_init_gart_aperture_regs() 148 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs() 150 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_1_init_gart_aperture_regs() 162 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_1_init_system_aperture_regs() 163 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_1_init_system_aperture_regs() [all …]
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D | gfx_v9_0.c | 154 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 155 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 156 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 157 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 158 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 159 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 160 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 161 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 162 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 163 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), [all …]
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D | gfxhub_v1_0.c | 36 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; in gfxhub_v1_0_get_mc_fb_offset() 45 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_setup_vm_pt_regs() 49 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_setup_vm_pt_regs() 69 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs() 71 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs() 74 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs() 76 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs() 79 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs() 81 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs() 84 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs() [all …]
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D | gfx_v9_4_3.c | 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), [all …]
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D | gfxhub_v3_0.c | 106 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); in gfxhub_v3_0_get_fb_location() 116 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; in gfxhub_v3_0_get_mc_fb_offset() 124 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v3_0_setup_vm_pt_regs() 128 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v3_0_setup_vm_pt_regs() 139 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v3_0_init_gart_aperture_regs() 141 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v3_0_init_gart_aperture_regs() 144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v3_0_init_gart_aperture_regs() 146 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v3_0_init_gart_aperture_regs() 155 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_init_system_aperture_regs() 156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs() [all …]
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D | gfxhub_v12_0.c | 113 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); in gfxhub_v12_0_get_fb_location() 123 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; in gfxhub_v12_0_get_mc_fb_offset() 132 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v12_0_setup_vm_pt_regs() 136 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v12_0_setup_vm_pt_regs() 147 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v12_0_init_gart_aperture_regs() 149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v12_0_init_gart_aperture_regs() 152 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v12_0_init_gart_aperture_regs() 154 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v12_0_init_gart_aperture_regs() 163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v12_0_init_system_aperture_regs() 164 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v12_0_init_system_aperture_regs() [all …]
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D | gfxhub_v11_5_0.c | 111 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); in gfxhub_v11_5_0_get_fb_location() 121 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; in gfxhub_v11_5_0_get_mc_fb_offset() 129 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v11_5_0_setup_vm_pt_regs() 133 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v11_5_0_setup_vm_pt_regs() 144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v11_5_0_init_gart_aperture_regs() 146 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v11_5_0_init_gart_aperture_regs() 149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v11_5_0_init_gart_aperture_regs() 151 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v11_5_0_init_gart_aperture_regs() 159 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v11_5_0_init_system_aperture_regs() 160 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v11_5_0_init_system_aperture_regs() [all …]
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D | gfxhub_v2_0.c | 107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_0_get_fb_location() 117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_0_get_mc_fb_offset() 125 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_0_setup_vm_pt_regs() 129 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_0_setup_vm_pt_regs() 140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs() 142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs() 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs() 147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs() 157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs() 158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs() [all …]
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D | gfxhub_v3_0_3.c | 109 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); in gfxhub_v3_0_3_get_fb_location() 119 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; in gfxhub_v3_0_3_get_mc_fb_offset() 127 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v3_0_3_setup_vm_pt_regs() 131 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v3_0_3_setup_vm_pt_regs() 142 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v3_0_3_init_gart_aperture_regs() 144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v3_0_3_init_gart_aperture_regs() 147 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v3_0_3_init_gart_aperture_regs() 149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v3_0_3_init_gart_aperture_regs() 161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_3_init_system_aperture_regs() 162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_3_init_system_aperture_regs() [all …]
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D | amdgpu_amdkfd_gfx_v9.c | 54 soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst)); in kgd_gfx_v9_lock_srbm() 59 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_unlock_srbm() 94 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings() 95 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings() 171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts() 238 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load() 241 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_load() 248 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_hqd_load() 277 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_hqd_load() 279 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_hqd_load() [all …]
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D | sdma_v5_0.c | 63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG), 64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM), 68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI), 69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH), 70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS), 71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS), 72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0), [all …]
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D | gfx_v11_0.c | 102 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 103 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 104 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), [all …]
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D | gfx_v12_0.c | 67 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), [all …]
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D | sdma_v7_0.c | 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), [all …]
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D | sdma_v6_0.c | 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), [all …]
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D | amdgpu_amdkfd_gfx_v10.c | 88 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); in kgd_program_sh_mem_settings() 89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings() 151 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in kgd_init_interrupts() 189 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) - 224 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load() 227 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load() 228 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in kgd_hqd_load() 234 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_hqd_load() 263 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in kgd_hqd_load() 265 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in kgd_hqd_load() [all …]
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D | sdma_v5_2.c | 64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM), 69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH), 71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS), 72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS), 73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0), [all …]
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D | amdgpu_amdkfd_gfx_v10_3.c | 88 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); in program_sh_mem_settings_v10_3() 89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in program_sh_mem_settings_v10_3() 120 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in init_interrupts_v10_3() 202 value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); in hqd_load_v10_3() 205 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value); in hqd_load_v10_3() 210 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_load_v10_3() 213 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v10_3() 214 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in hqd_load_v10_3() 220 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); in hqd_load_v10_3() 249 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in hqd_load_v10_3() [all …]
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