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Searched refs:Fld (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/arch/arm/mach-sa1100/include/mach/
DSA-1100.h137 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
139 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
145 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
177 #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
179 #define UDCWC_WC Fld (4, 0) /* Write Count */
181 #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
337 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
338 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
378 #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
474 #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
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Dbitfield.h46 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
/linux-6.12.1/drivers/video/fbdev/
Dpxa3xx-regs.h87 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
93 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
99 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
102 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
105 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */
108 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
111 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
127 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
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/linux-6.12.1/arch/arm/include/asm/hardware/
Dsa1111.h65 #define SMCR_DRAC Fld(3, 2)