1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016-2017 Google, Inc
4  *
5  * Fairchild FUSB302 Type-C Chip Driver
6  */
7 
8 #ifndef FUSB302_REG_H
9 #define FUSB302_REG_H
10 
11 #define FUSB_REG_DEVICE_ID			0x01
12 #define FUSB_REG_SWITCHES0			0x02
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN		BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN		BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2		BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1		BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2		BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1		BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN		BIT(1)
20 #define FUSB_REG_SWITCHES0_CC1_PD_EN		BIT(0)
21 #define FUSB_REG_SWITCHES1			0x03
22 #define FUSB_REG_SWITCHES1_POWERROLE		BIT(7)
23 #define FUSB_REG_SWITCHES1_SPECREV1		BIT(6)
24 #define FUSB_REG_SWITCHES1_SPECREV0		BIT(5)
25 #define FUSB_REG_SWITCHES1_DATAROLE		BIT(4)
26 #define FUSB_REG_SWITCHES1_AUTO_GCRC		BIT(2)
27 #define FUSB_REG_SWITCHES1_TXCC2_EN		BIT(1)
28 #define FUSB_REG_SWITCHES1_TXCC1_EN		BIT(0)
29 #define FUSB_REG_MEASURE			0x04
30 #define FUSB_REG_MEASURE_MDAC5			BIT(7)
31 #define FUSB_REG_MEASURE_MDAC4			BIT(6)
32 #define FUSB_REG_MEASURE_MDAC3			BIT(5)
33 #define FUSB_REG_MEASURE_MDAC2			BIT(4)
34 #define FUSB_REG_MEASURE_MDAC1			BIT(3)
35 #define FUSB_REG_MEASURE_MDAC0			BIT(2)
36 #define FUSB_REG_MEASURE_VBUS			BIT(1)
37 #define FUSB_REG_MEASURE_XXXX5			BIT(0)
38 #define FUSB_REG_CONTROL0			0x06
39 #define FUSB_REG_CONTROL0_TX_FLUSH		BIT(6)
40 #define FUSB_REG_CONTROL0_INT_MASK		BIT(5)
41 #define FUSB_REG_CONTROL0_HOST_CUR_MASK		(0xC)
42 #define FUSB_REG_CONTROL0_HOST_CUR_HIGH		(0xC)
43 #define FUSB_REG_CONTROL0_HOST_CUR_MED		(0x8)
44 #define FUSB_REG_CONTROL0_HOST_CUR_DEF		(0x4)
45 #define FUSB_REG_CONTROL0_TX_START		BIT(0)
46 #define FUSB_REG_CONTROL1			0x07
47 #define FUSB_REG_CONTROL1_ENSOP2DB		BIT(6)
48 #define FUSB_REG_CONTROL1_ENSOP1DB		BIT(5)
49 #define FUSB_REG_CONTROL1_BIST_MODE2		BIT(4)
50 #define FUSB_REG_CONTROL1_RX_FLUSH		BIT(2)
51 #define FUSB_REG_CONTROL1_ENSOP2		BIT(1)
52 #define FUSB_REG_CONTROL1_ENSOP1		BIT(0)
53 #define FUSB_REG_CONTROL2			0x08
54 #define FUSB_REG_CONTROL2_MODE			BIT(1)
55 #define FUSB_REG_CONTROL2_MODE_MASK		(0x6)
56 #define FUSB_REG_CONTROL2_MODE_DFP		(0x6)
57 #define FUSB_REG_CONTROL2_MODE_UFP		(0x4)
58 #define FUSB_REG_CONTROL2_MODE_DRP		(0x2)
59 #define FUSB_REG_CONTROL2_MODE_NONE		(0x0)
60 #define FUSB_REG_CONTROL2_TOGGLE		BIT(0)
61 #define FUSB_REG_CONTROL3			0x09
62 #define FUSB_REG_CONTROL3_SEND_HARDRESET	BIT(6)
63 #define FUSB_REG_CONTROL3_BIST_TMODE		BIT(5)	/* 302B Only */
64 #define FUSB_REG_CONTROL3_AUTO_HARDRESET	BIT(4)
65 #define FUSB_REG_CONTROL3_AUTO_SOFTRESET	BIT(3)
66 #define FUSB_REG_CONTROL3_N_RETRIES		BIT(1)
67 #define FUSB_REG_CONTROL3_N_RETRIES_MASK	(0x6)
68 #define FUSB_REG_CONTROL3_N_RETRIES_3		(0x6)
69 #define FUSB_REG_CONTROL3_N_RETRIES_2		(0x4)
70 #define FUSB_REG_CONTROL3_N_RETRIES_1		(0x2)
71 #define FUSB_REG_CONTROL3_AUTO_RETRY		BIT(0)
72 #define FUSB_REG_MASK				0x0A
73 #define FUSB_REG_MASK_VBUSOK			BIT(7)
74 #define FUSB_REG_MASK_ACTIVITY			BIT(6)
75 #define FUSB_REG_MASK_COMP_CHNG			BIT(5)
76 #define FUSB_REG_MASK_CRC_CHK			BIT(4)
77 #define FUSB_REG_MASK_ALERT			BIT(3)
78 #define FUSB_REG_MASK_WAKE			BIT(2)
79 #define FUSB_REG_MASK_COLLISION			BIT(1)
80 #define FUSB_REG_MASK_BC_LVL			BIT(0)
81 #define FUSB_REG_POWER				0x0B
82 #define FUSB_REG_POWER_PWR			BIT(0)
83 #define FUSB_REG_POWER_PWR_LOW			0x1
84 #define FUSB_REG_POWER_PWR_MEDIUM		0x3
85 #define FUSB_REG_POWER_PWR_HIGH			0x7
86 #define FUSB_REG_POWER_PWR_ALL			0xF
87 #define FUSB_REG_RESET				0x0C
88 #define FUSB_REG_RESET_PD_RESET			BIT(1)
89 #define FUSB_REG_RESET_SW_RESET			BIT(0)
90 #define FUSB_REG_MASKA				0x0E
91 #define FUSB_REG_MASKA_OCP_TEMP			BIT(7)
92 #define FUSB_REG_MASKA_TOGDONE			BIT(6)
93 #define FUSB_REG_MASKA_SOFTFAIL			BIT(5)
94 #define FUSB_REG_MASKA_RETRYFAIL		BIT(4)
95 #define FUSB_REG_MASKA_HARDSENT			BIT(3)
96 #define FUSB_REG_MASKA_TX_SUCCESS		BIT(2)
97 #define FUSB_REG_MASKA_SOFTRESET		BIT(1)
98 #define FUSB_REG_MASKA_HARDRESET		BIT(0)
99 #define FUSB_REG_MASKB				0x0F
100 #define FUSB_REG_MASKB_GCRCSENT			BIT(0)
101 #define FUSB_REG_STATUS0A			0x3C
102 #define FUSB_REG_STATUS0A_SOFTFAIL		BIT(5)
103 #define FUSB_REG_STATUS0A_RETRYFAIL		BIT(4)
104 #define FUSB_REG_STATUS0A_POWER			BIT(2)
105 #define FUSB_REG_STATUS0A_RX_SOFT_RESET		BIT(1)
106 #define FUSB_REG_STATUS0A_RX_HARD_RESET		BIT(0)
107 #define FUSB_REG_STATUS1A			0x3D
108 #define FUSB_REG_STATUS1A_TOGSS			BIT(3)
109 #define FUSB_REG_STATUS1A_TOGSS_RUNNING		0x0
110 #define FUSB_REG_STATUS1A_TOGSS_SRC1		0x1
111 #define FUSB_REG_STATUS1A_TOGSS_SRC2		0x2
112 #define FUSB_REG_STATUS1A_TOGSS_SNK1		0x5
113 #define FUSB_REG_STATUS1A_TOGSS_SNK2		0x6
114 #define FUSB_REG_STATUS1A_TOGSS_AA		0x7
115 #define FUSB_REG_STATUS1A_TOGSS_POS		(3)
116 #define FUSB_REG_STATUS1A_TOGSS_MASK		(0x7)
117 #define FUSB_REG_STATUS1A_RXSOP2DB		BIT(2)
118 #define FUSB_REG_STATUS1A_RXSOP1DB		BIT(1)
119 #define FUSB_REG_STATUS1A_RXSOP			BIT(0)
120 #define FUSB_REG_INTERRUPTA			0x3E
121 #define FUSB_REG_INTERRUPTA_OCP_TEMP		BIT(7)
122 #define FUSB_REG_INTERRUPTA_TOGDONE		BIT(6)
123 #define FUSB_REG_INTERRUPTA_SOFTFAIL		BIT(5)
124 #define FUSB_REG_INTERRUPTA_RETRYFAIL		BIT(4)
125 #define FUSB_REG_INTERRUPTA_HARDSENT		BIT(3)
126 #define FUSB_REG_INTERRUPTA_TX_SUCCESS		BIT(2)
127 #define FUSB_REG_INTERRUPTA_SOFTRESET		BIT(1)
128 #define FUSB_REG_INTERRUPTA_HARDRESET		BIT(0)
129 #define FUSB_REG_INTERRUPTB			0x3F
130 #define FUSB_REG_INTERRUPTB_GCRCSENT		BIT(0)
131 #define FUSB_REG_STATUS0			0x40
132 #define FUSB_REG_STATUS0_VBUSOK			BIT(7)
133 #define FUSB_REG_STATUS0_ACTIVITY		BIT(6)
134 #define FUSB_REG_STATUS0_COMP			BIT(5)
135 #define FUSB_REG_STATUS0_CRC_CHK		BIT(4)
136 #define FUSB_REG_STATUS0_ALERT			BIT(3)
137 #define FUSB_REG_STATUS0_WAKE			BIT(2)
138 #define FUSB_REG_STATUS0_BC_LVL_MASK		0x03
139 #define FUSB_REG_STATUS0_BC_LVL_0_200		0x0
140 #define FUSB_REG_STATUS0_BC_LVL_200_600		0x1
141 #define FUSB_REG_STATUS0_BC_LVL_600_1230	0x2
142 #define FUSB_REG_STATUS0_BC_LVL_1230_MAX	0x3
143 #define FUSB_REG_STATUS0_BC_LVL1		BIT(1)
144 #define FUSB_REG_STATUS0_BC_LVL0		BIT(0)
145 #define FUSB_REG_STATUS1			0x41
146 #define FUSB_REG_STATUS1_RXSOP2			BIT(7)
147 #define FUSB_REG_STATUS1_RXSOP1			BIT(6)
148 #define FUSB_REG_STATUS1_RX_EMPTY		BIT(5)
149 #define FUSB_REG_STATUS1_RX_FULL		BIT(4)
150 #define FUSB_REG_STATUS1_TX_EMPTY		BIT(3)
151 #define FUSB_REG_STATUS1_TX_FULL		BIT(2)
152 #define FUSB_REG_INTERRUPT			0x42
153 #define FUSB_REG_INTERRUPT_VBUSOK		BIT(7)
154 #define FUSB_REG_INTERRUPT_ACTIVITY		BIT(6)
155 #define FUSB_REG_INTERRUPT_COMP_CHNG		BIT(5)
156 #define FUSB_REG_INTERRUPT_CRC_CHK		BIT(4)
157 #define FUSB_REG_INTERRUPT_ALERT		BIT(3)
158 #define FUSB_REG_INTERRUPT_WAKE			BIT(2)
159 #define FUSB_REG_INTERRUPT_COLLISION		BIT(1)
160 #define FUSB_REG_INTERRUPT_BC_LVL		BIT(0)
161 #define FUSB_REG_FIFOS				0x43
162 
163 /* Tokens defined for the FUSB302 TX FIFO */
164 enum fusb302_txfifo_tokens {
165 	FUSB302_TKN_TXON = 0xA1,
166 	FUSB302_TKN_SYNC1 = 0x12,
167 	FUSB302_TKN_SYNC2 = 0x13,
168 	FUSB302_TKN_SYNC3 = 0x1B,
169 	FUSB302_TKN_RST1 = 0x15,
170 	FUSB302_TKN_RST2 = 0x16,
171 	FUSB302_TKN_PACKSYM = 0x80,
172 	FUSB302_TKN_JAMCRC = 0xFF,
173 	FUSB302_TKN_EOP = 0x14,
174 	FUSB302_TKN_TXOFF = 0xFE,
175 };
176 
177 #endif
178