| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| D | dcn401_dpp.c | 75 REG_SET_2(FORMAT_CONTROL, 0, in dpp401_dpp_setup()
79 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp401_dpp_setup()
80 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp401_dpp_setup()
81 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp401_dpp_setup()
82 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp401_dpp_setup()
84 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); in dpp401_dpp_setup()
85 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); in dpp401_dpp_setup()
86 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); in dpp401_dpp_setup()
193 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp401_dpp_setup()
|
| D | dcn401_dpp_cm.c | 100 REG_SET_3(FORMAT_CONTROL, 0, in dpp401_full_bypass()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| D | dcn201_dpp.c | 60 REG_SET_2(FORMAT_CONTROL, 0, in dpp201_cnv_setup()
71 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp201_cnv_setup()
72 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp201_cnv_setup()
73 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp201_cnv_setup()
74 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp201_cnv_setup()
175 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| D | dcn20_dpp.c | 115 REG_SET_2(FORMAT_CONTROL, 0, in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
126 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
127 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
229 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp2_cnv_setup()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| D | dcn30_dpp.c | 225 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
229 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp3_cnv_setup()
230 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp3_cnv_setup()
231 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp3_cnv_setup()
232 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp3_cnv_setup()
234 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); in dpp3_cnv_setup()
235 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); in dpp3_cnv_setup()
236 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); in dpp3_cnv_setup()
347 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp3_cnv_setup()
|
| D | dcn30_dpp.h | 137 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| D | dcn10_dpp.c | 304 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
310 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
382 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
|
| D | dcn10_dpp_cm.c | 780 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
|
| D | dcn10_dpp.h | 120 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
1343 uint32_t FORMAT_CONTROL; \
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_ipp.h | 35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
189 uint32_t FORMAT_CONTROL; member
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| D | dcn401_resource.h | 312 SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource.h | 510 SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \
|