/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_opp.h | 45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 87 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 101 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 102 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 103 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 104 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 105 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 106 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 107 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 108 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ [all …]
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D | dce_opp.c | 109 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation() 118 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation() 124 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation() 134 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation() 156 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation() 163 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation() 168 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation() 177 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation() 204 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither() 209 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/opp/dcn10/ |
D | dcn10_opp.c | 54 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in opp1_set_truncation() 65 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither() 122 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
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D | dcn10_opp.h | 37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 54 uint32_t FMT_BIT_DEPTH_CONTROL; \
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | dce_v10_0.c | 537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt() 538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt() 539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt() 540 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v10_0_program_fmt() 542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt() 543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v10_0_program_fmt() 549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt() 550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt() 551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt() 552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt() [all …]
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D | dce_v11_0.c | 569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt() 570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt() 571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt() 572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v11_0_program_fmt() 574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt() 575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v11_0_program_fmt() 581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt() 582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt() 583 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt() 584 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt() [all …]
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D | sid.h | 2104 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 macro
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/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | cikd.h | 987 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
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D | evergreend.h | 1376 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
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D | r600d.h | 1245 #define FMT_BIT_DEPTH_CONTROL 0x6710 macro
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D | r600.c | 346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
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D | evergreen.c | 1345 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
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D | cik.c | 8784 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
D | dcn32_resource.h | 537 SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \
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