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Searched refs:FIELD_SET (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_tuning.c32 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
37 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
70 XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
75 XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
112 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
131 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
139 XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
Dxe_hw_engine.c378 XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0), in xe_hw_engine_setup_default_lrc_state()
387 XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE, in xe_hw_engine_setup_default_lrc_state()
393 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0), in xe_hw_engine_setup_default_lrc_state()
429 XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0), in hw_engine_setup_default_state()
446 FIELD_SET(RING_PWRCTX_MAXCNT(0), in hw_engine_setup_default_state()
Dxe_wa.c340 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
581 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
616 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
/linux-6.12.1/drivers/soc/qcom/
Dspm.c26 #define FIELD_SET(current, mask, val) \ macro
355 vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); in smp_set_vdd_v1_1()
356 data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); in smp_set_vdd_v1_1()
357 data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MIN_VSEL, volt_sel); in smp_set_vdd_v1_1()
358 data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MAX_VSEL, volt_sel); in smp_set_vdd_v1_1()
376 avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); in smp_set_vdd_v1_1()
377 avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); in smp_set_vdd_v1_1()
/linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/
Dcgx.c911 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); in cgx_lmac_pause_frm_config()
979 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg); in cgx_lmac_pfc_config()
982 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); in cgx_lmac_pfc_config()
1061 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req); in cgx_fwi_cmd_send()
1437 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req); in cgx_get_fwdata_base()
1459 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req); in cgx_set_link_mode()
1460 req = FIELD_SET(CMDMODECHANGE_SPEED, in cgx_set_link_mode()
1462 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req); in cgx_set_link_mode()
1463 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req); in cgx_set_link_mode()
1464 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req); in cgx_set_link_mode()
[all …]
Drpm.c393 cfg = FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg); in rpm_lmac_pause_frm_config()
469 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_LINK_STS, req); in rpm_get_lmac_type()
655 class_en = FIELD_SET(RPM_PFC_CLASS_MASK, pfc_en, class_en); in rpm_lmac_pfc_config()
659 class_en = FIELD_SET(RPM_PFC_CLASS_MASK, 0, class_en); in rpm_lmac_pfc_config()
Dcgx_fw_if.h159 #define FIELD_SET(m, y, x) \ macro
/linux-6.12.1/drivers/gpu/drm/xe/tests/
Dxe_rtp_test.c229 XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,